MultiReg false path issue?

[diorcety]

Vivado, artix-7

I'm trying to figure the need to use

            if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
                self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
                if not eth_rx_clk is eth_tx_clk:
                    self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
                    self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
                else:
                    self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk)

LiteEthMACCore uses ClockDomainCrossing and is backed by the add_platform_command on mr_ff == TRUE. It should be enough, no? https://github.com/enjoy-digital/litex/blob/master/litex/build/xilinx/vivado.py#L196

When disabling the false_path_constraints using with_timing_constraints = False, the timing report exactly matches the issue on the paths to the first FF of the 2FF used for CDC. The set_false_path seems useless.
The platform command shouldn't be the next one?

        self.platform.add_platform_command(
            "set_false_path -quiet "
            "-to [get_cells -hierarchical -filter {{mr_ff == TRUE}}]"
        )