SD1 PS peripheral not supported in Zynq-7000

[gkirilow-motec]

We are currently working on a project where we would like to use SD1 as an EMIO but noticed no references to SD1 in the generation scripts. SD0 is handled as below in

        # SDIO0 ------------------------------------------------------------------------------------
        ps7_sdio0_pads = platform.request("ps7_sdio0", loose=True, reserve=self.reserve_pads)
        if ps7_sdio0_pads is not None:
            self.cpu_params.update(
                o_SDIO0_CLK     = ps7_sdio0_pads.clk,
                i_SDIO0_CLK_FB  = ps7_sdio0_pads.clk_fb,
                o_SDIO0_CMD_O   = ps7_sdio0_pads.cmd_o,
                i_SDIO0_CMD_I   = ps7_sdio0_pads.cmd_i,
                o_SDIO0_CMD_T   = ps7_sdio0_pads.cmd_t,
                o_SDIO0_DATA_O  = ps7_sdio0_pads.data_o,
                i_SDIO0_DATA_I  = ps7_sdio0_pads.data_i,
                o_SDIO0_DATA_T  = ps7_sdio0_pads.data_t,
                o_SDIO0_LED     = ps7_sdio0_pads.led,
                o_SDIO0_BUSPOW  = ps7_sdio0_pads.buspow,
                o_SDIO0_BUSVOLT = ps7_sdio0_pads.busvolt,
            )

        # SDIO0_CD ---------------------------------------------------------------------------------
        ps7_sdio0_cd_pads = platform.request("ps7_sdio0_cd", loose=True, reserve=self.reserve_pads)
        if ps7_sdio0_cd_pads is not None:
            self.cpu_params.update(i_SDIO0_CDN = ps7_sdio0_cd_pads.cdn)

        # SDIO0_WP ---------------------------------------------------------------------------------
        ps7_sdio0_wp_pads = platform.request("ps7_sdio0_wp", loose=True, reserve=self.reserve_pads)
        if ps7_sdio0_wp_pads is not None:
            self.cpu_params.update(i_SDIO0_WP = ps7_sdio0_wp_pads.wp)

Which we use perfectly fine for SD0 booting.

Is this a known gap that is planned to be supported?

Above snippet is from litex/litex/soc/cores/cpu/zynq7000/core.py

We were attempting to integrate SD1 using:

"PCW_SD1_PERIPHERAL_ENABLE"             : "1",
"PCW_SD1_SD1_IO"                        : "EMIO",
"PCW_SD1_GRP_CD_ENABLE"                 : "0",
"PCW_SD1_GRP_WP_ENABLE"                 : "0",

sd1_pads = platform.request("sd",1)

It could also be a misunderstanding in how it should be integrated though?

Thanks,
Glenn

[trabucayre]

Hi @gkirilow-motec In fact this piece of code doesn't make sense: when SDx is used via MIO signals are not present in the PS wrapper. Only signals using EMIO are present. When SD0 or SD1 are used fully with MIO the only requirement is some lines of TCL to configure the processing_system IP (usually this is done at platform level).

I have some code locally to adds support for SDIO with a method called def add_sdio in soc/cores/cpu/zynq7000/core.py. I have to validates all combinaison before creates a PR.

[gkirilow-motec]

Hi @trabucayre, I'm not sure what doesn't make sense sorry? In our usecase we use SD0 as MIO for SD boot and wish to use SD1 for EMIO? Perhaps I'm misunderstanding. Okay, thanks for clarifying that regarding the TCL.

Thanks, I'll take a look.

[trabucayre]

Your use case is fine. Sorry my answer is not really clear.
the problem I mention is related to the piece of code in zynq7000/core.py constructor:

• this code assume SDIO0 must be used: it's not possible to select between SDIO0 or SDIO1
• ps7_config (tcl sequence) is not updated to enable this controler
• this set of pins is only available when the controler is configured to uses EMIO and absent otherwise
• no IOBUF for cmd and data (this is fine with Vivado block design because the tool will automagically adding IOBUF primitives when generating top module).

I have a open PR to adds more cleanly SDIO support here #2365

For example, in a zynq target:

# add sdio0 via MIO (Interface with 40..45, CD: MIO 47, WP: MIO 53, Power: MIO 0)
self.cpu.add_sdio(0, "MIO 40 .. 45", "MIO 47", "MIO 53", "MIO 0")
# add sdio1 via EMIO (all signals comes from sdio_emio resource, CD/WP must left to None, Power is unused here)
self.cpu.add_sdio(1, platform.request("sdio_emio"))

[gkirilow-motec]

Ah I see, thanks for clarifying and raising the PR :)

[gkirilow-motec]

Hi, this issue has not been fixed. In the generated verilog code while I see SD1 connections, I cannot see them hooked up to the ps7 instantiation as below:

module alinx_ax7020 (
    input  wire          can0_irq,
    input  wire          can0_rx,
    output wire          can0_tx,
    input  wire          can1_irq,
    input  wire          can1_rx,
    output wire          can1_tx,
    inout  wire          i2c0_scl,
    inout  wire          i2c0_sda,
    inout  wire          ps7_clk,
    inout  wire   [14:0] ps7_ddram_addr,
    inout  wire    [2:0] ps7_ddram_ba,
    inout  wire          ps7_ddram_cas_n,
    inout  wire          ps7_ddram_ck_n,
    inout  wire          ps7_ddram_ck_p,
    inout  wire          ps7_ddram_cke,
    inout  wire          ps7_ddram_cs_n,
    inout  wire    [3:0] ps7_ddram_dm,
    inout  wire   [31:0] ps7_ddram_dq,
    inout  wire    [3:0] ps7_ddram_dqs_n,
    inout  wire    [3:0] ps7_ddram_dqs_p,
    inout  wire          ps7_ddram_odt,
    inout  wire          ps7_ddram_ras_n,
    inout  wire          ps7_ddram_reset_n,
    inout  wire          ps7_ddram_vrn,
    inout  wire          ps7_ddram_vrp,
    inout  wire          ps7_ddram_we_n,
    inout  wire   [53:0] ps7_mio,
    inout  wire          ps7_porb,
    inout  wire          ps7_srstb,
    input  wire          sd1_clk,
    input  wire          sd1_cmd,
    input  wire    [3:0] sd1_data,
    output wire          user_led0,
    output wire          user_led1,
    output wire          user_led2,
    output wire          user_led3
);

//------------------------------------------------------------------------------
// Instance Zynq of Zynq Module.
//------------------------------------------------------------------------------
Zynq Zynq(
// Inputs.
.GPIO_I (main_cpu_emio_pads_i),
.IRQ_F2P (main_cpu_interrupt),
.M_AXI_GP0_ACLK (ps7_clk_1),
.M_AXI_GP0_ARREADY (main_cpu_ar_ready),
.M_AXI_GP0_AWREADY (main_cpu_aw_ready),
.M_AXI_GP0_BID (main_cpu_b_param_id),
.M_AXI_GP0_BRESP (main_cpu_b_payload_resp),
.M_AXI_GP0_BVALID (main_cpu_b_valid),
.M_AXI_GP0_RDATA (main_cpu_r_payload_data),
.M_AXI_GP0_RID (main_cpu_r_param_id),
.M_AXI_GP0_RLAST (main_cpu_r_last),
.M_AXI_GP0_RRESP (main_cpu_r_payload_resp),
.M_AXI_GP0_RVALID (main_cpu_r_valid),
.M_AXI_GP0_WREADY (main_cpu_w_ready),
.USB0_VBUS_PWRFAULT (1'd0),

// Outputs.
.FCLK_CLK0          (ps7_clk_1),
.FCLK_RESET0_N      (main_cpu_ps7_rst_n),
.GPIO_O             (main_cpu_emio_pads_o),
.GPIO_T             (main_cpu_emio_pads_t),
.M_AXI_GP0_ARADDR   (main_cpu_ar_payload_addr),
.M_AXI_GP0_ARBURST  (main_cpu_ar_payload_burst),
.M_AXI_GP0_ARCACHE  (main_cpu_ar_payload_cache),
.M_AXI_GP0_ARID     (main_cpu_ar_param_id),
.M_AXI_GP0_ARLEN    (main_cpu_ar_payload_len),
.M_AXI_GP0_ARLOCK   (main_cpu_ar_payload_lock),
.M_AXI_GP0_ARPROT   (main_cpu_ar_payload_prot),
.M_AXI_GP0_ARQOS    (main_cpu_ar_payload_qos),
.M_AXI_GP0_ARSIZE   (main_cpu_ar_payload_size),
.M_AXI_GP0_ARVALID  (main_cpu_ar_valid),
.M_AXI_GP0_AWADDR   (main_cpu_aw_payload_addr),
.M_AXI_GP0_AWBURST  (main_cpu_aw_payload_burst),
.M_AXI_GP0_AWCACHE  (main_cpu_aw_payload_cache),
.M_AXI_GP0_AWID     (main_cpu_aw_param_id),
.M_AXI_GP0_AWLEN    (main_cpu_aw_payload_len),
.M_AXI_GP0_AWLOCK   (main_cpu_aw_payload_lock),
.M_AXI_GP0_AWPROT   (main_cpu_aw_payload_prot),
.M_AXI_GP0_AWQOS    (main_cpu_aw_payload_qos),
.M_AXI_GP0_AWSIZE   (main_cpu_aw_payload_size),
.M_AXI_GP0_AWVALID  (main_cpu_aw_valid),
.M_AXI_GP0_BREADY   (main_cpu_b_ready),
.M_AXI_GP0_RREADY   (main_cpu_r_ready),
.M_AXI_GP0_WDATA    (main_cpu_w_payload_data),
.M_AXI_GP0_WID      (main_cpu_w_param_id),
.M_AXI_GP0_WLAST    (main_cpu_w_last),
.M_AXI_GP0_WSTRB    (main_cpu_w_payload_strb),
.M_AXI_GP0_WVALID   (main_cpu_w_valid),

// InOuts.
.DDR_Addr           (ps7_ddram_addr),
.DDR_BankAddr       (ps7_ddram_ba),
.DDR_CAS_n          (ps7_ddram_cas_n),
.DDR_CKE            (ps7_ddram_cke),
.DDR_CS_n           (ps7_ddram_cs_n),
.DDR_Clk            (ps7_ddram_ck_p),
.DDR_Clk_n          (ps7_ddram_ck_n),
.DDR_DM             (ps7_ddram_dm),
.DDR_DQ             (ps7_ddram_dq),
.DDR_DQS            (ps7_ddram_dqs_p),
.DDR_DQS_n          (ps7_ddram_dqs_n),
.DDR_DRSTB          (ps7_ddram_reset_n),
.DDR_ODT            (ps7_ddram_odt),
.DDR_RAS_n          (ps7_ddram_ras_n),
.DDR_VRN            (ps7_ddram_vrn),
.DDR_VRP            (ps7_ddram_vrp),
.DDR_WEB            (ps7_ddram_we_n),
.MIO                (ps7_mio),
.PS_CLK             (ps7_clk),
.PS_PORB            (ps7_porb),
.PS_SRSTB           (ps7_srstb)

);

[trabucayre]

Weird.
Have you an up-to-date LiteX?
In you code I see:

input  wire          sd1_clk,
input  wire          sd1_cmd,
input  wire    [3:0] sd1_data,

But when I check verilog produces for a digilent_arty_z7 with a digilent microSD PMOD I see:

input  wire          sdcard_cd,
output wire          sdcard_clk,
inout  wire          sdcard_cmd,
inout  wire    [3:0] sdcard_data,

You don't have the card detect signal (not a problem) but your cmd and data are input instead of inout.

Also the Zynq primitive looks like:

Zynq Zynq(
    // Inputs.
[...]
    .SDIO1_CDN          (sdcard_cd),
    .SDIO1_CLK_FB       (sdcard_clk),
    .SDIO1_CMD_I        (zynq7000_sd_cmd_i),
    .SDIO1_DATA_I       (zynq7000_sd_data_i),
    .SDIO1_WP           (1'd0),
    .USB0_VBUS_PWRFAULT (1'd0),

    // Outputs.
[...]
    .SDIO1_BUSPOW       (zynq70001),
    .SDIO1_BUSVOLT      (zynq70002),
    .SDIO1_CLK          (sdcard_clk),
    .SDIO1_CMD_O        (zynq7000_sd_cmd_o),
    .SDIO1_CMD_T        (zynq7000_sd_cmd_oe),
    .SDIO1_DATA_O       (zynq7000_sd_data_o),
    .SDIO1_DATA_T       (zynq7000_sd_data_t),
    .SDIO1_LED          (zynq70000),
[...]

For reference modifications apply to the arty z7 board are:

# beginning of the file
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc

# Somewhere in BaseSoC __init__ method
platform.add_extension([
    ("sdcard", 0,
        Subsignal("data", Pins("pmoda:2 pmoda:4 pmoda:5 pmoda:0"), Misc("SLEW=FAST"), Misc("PULLUP True")),
        Subsignal("cmd",  Pins("pmoda:1"), Misc("SLEW=FAST"), Misc("PULLUP True")),
        Subsignal("clk",  Pins("pmoda:3"), Misc("SLEW=FAST")),
        Subsignal("cd",   Pins("pmoda:6")),
        IOStandard("LVCMOS33"),
    ),
])

# SDIO1 via EMIO
self.cpu.add_sdio(1, platform.request("sdcard"))

Could you share your code? Or at least the relevant part?
Thanks

[gkirilow-motec]

We are using an alinx_ax7020 development board.

I may have misunderstood, doing the following now generates the PS7 instance as expected:
("sd", 1, Subsignal("clk", Pins("U14"), Misc("SLEW=FAST")), Subsignal("cmd", Pins("V20"), Misc("SLEW=FAST"), Misc("PULLUP True")), Subsignal("data", Pins("V15 V16 V17 V18"), Misc("SLEW=FAST"), Misc("PULLUP True")), Subsignal("cd", Pins("W20")), IOStandard("LVCMOS33") ),

# SDIO1 ------------------------------------------------------------------------------------ # Connect EMIO ports to top-level pins sd1_pads = platform.request("sd", 1) # SDIO1 via EMIO self.cpu.add_sdio(1, sd1_pads)

I won't close the issue yet as I need to try it on an actual board and verify that mmcblk1 appears. Hopefully should have a microsd card reader in to test later this week if not early next week. We will keep you posted.

Thanks for the support.