support responder clock stretching when Rx FIFO full

[incanus]

This adds (optional) support for responder-side clock stretching when the Rx FIFO is full.

A good explanation of the feature is here:

While control of the SCL line is the domain of the I2C master, an optional feature of the protocol allows slaves to temporarily control it to slow down transmission before it is ready to accept more data.

To stretch the clock, the slave device simply holds the SCL line down. In that state, the master device must wait for the clock rises back up to high before resuming transmission.

[incanus]

Here's a bit more from the Pi forums related to the C equivalent:

This instructs DW_apb_i2c to hold SCL low while the RX FIFO is full, preventing the master from transmitting more bytes (and overrunning the FIFO) until the ISR has time to handle things.