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support responder clock stretching when Rx FIFO full #5

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support responder clock stretching when Rx FIFO full #5

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6 changes: 5 additions & 1 deletion i2c_responder.py
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Original file line number Diff line number Diff line change
Expand Up @@ -57,6 +57,7 @@ class I2CResponder:
IC_CON__CONTROLLER_MODE = 0x01
IC_CON__IC_10BITADDR_RESPONDER = 0x08
IC_CON__IC_RESPONDER_DISABLE = 0x40
IC_CON__RX_FIFO_FULL_HLD_CTRL = 0x200
GPIOxCTRL__FUNCSEL = 0x1F
GPIOxCTRL__FUNCSEL__I2C = 3

Expand All @@ -72,7 +73,7 @@ def clr_reg(self, register_offset, data):
"""Clear bits in Pico register."""
self.write_reg(register_offset, data, method=self.REG_ACCESS_METHOD_CLR)

def __init__(self, i2c_device_id=0, sda_gpio=0, scl_gpio=1, responder_address=0x41):
def __init__(self, i2c_device_id=0, sda_gpio=0, scl_gpio=1, responder_address=0x41, clock_stretching=False):
"""Initialize.

Args:
Expand All @@ -94,6 +95,9 @@ def __init__(self, i2c_device_id=0, sda_gpio=0, scl_gpio=1, responder_address=0x
self.set_reg(self.IC_SAR, self.responder_address & self.IC_SAR__IC_SAR)
# Clear 10 Bit addressing bit (i.e. enable 7 bit addressing)
# Clear CONTROLLER bit (i.e. we are a Responder)
# Enable clock stretching?
if clock_stretching:
self.set_reg(self.IC_CON, self.IC_CON__RX_FIFO_FULL_HLD_CTRL)
# Clear RESPONDER_DISABLE bit (i.e. we are a Responder)
self.clr_reg(
self.IC_CON,
Expand Down