Improve SVE2 optimizations of Gemm32fNT - #827
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Rewrite Gemm32fNT microkernels with explicit NEON/AVX512-style code, unpredicated svmla_f32_x in the main loops, dual accumulators where register pressure allows, and a correct F-sized remainder before the masked tail. Document the change under release 7.2.165. Co-authored-by: Ihar Yermalayeu <ermig1979@gmail.com>
ermig1979
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August 6, 2026 09:55
This was referenced Aug 6, 2026
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Summary
Improves ARM SVE/SVE2 optimizations of
SimdGemm32fNTinSimdSve2Gemm32fNT.cppand documents the change under release 7.2.165.Changes
SIMD_SVE2_GEMM_*macros; expand microkernels to explicit code matching the NEON/AVX-512BW style.svmla_f32_xin full-vector body loops instead of always-predicatedsvmla_f32_m.F-wide chunk after the DF loop before the masked tail (previously a single masked step could drop lanes when remainingKwas in(F, 2F)).Add4ExtractedSumshelper for 4-column kernels.docs/2026.html(release 7.2.165 Algorithms → Improving).Validation
./Test "-r=.." -fi=Gemm32fNT -tt=1 -ts=1— passed.-DSIMD_SVE2=ON:Simd::Sve2::Gemm32fNTlinked inlibSimd.so.-cpu max,sve=on, VL=512):Gemm32fNTAutoTest passed for Base/NEON/SVE2, including odd-Kshapes that exercise the remainder path.