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arcv: Fix arcv.vclr intrinsic signature.#206

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arcv: Fix arcv.vclr intrinsic signature.#206
luismgsilva wants to merge 2 commits into
arc-2026.03from
luis/fix-vclr

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@luismgsilva luismgsilva commented Feb 5, 2026

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The arcv.vclr instruction takes (imm, vl) in the base variant and
(vector, imm, vl) for tail-undisturbed. We add a custom shape and
expand method to handle both cases.

@luismgsilva luismgsilva self-assigned this Feb 5, 2026
@luismgsilva luismgsilva force-pushed the luis/fix-vclr branch 5 times, most recently from ea81b05 to 5ff7742 Compare February 5, 2026 16:48
@luismgsilva luismgsilva changed the title tmp: arcv: Fix vclr intrinsic. arcv: Fix arcv.vclr intrinsic signature. Feb 5, 2026
@luismgsilva luismgsilva force-pushed the luis/fix-vclr branch 6 times, most recently from ec063e0 to 5d8bcac Compare February 9, 2026 11:37
@luismgsilva luismgsilva marked this pull request as ready for review February 9, 2026 11:37
Comment thread gcc/config/riscv/riscv-vector-builtins-bases.cc Outdated
@luismgsilva luismgsilva force-pushed the luis/fix-vclr branch 2 times, most recently from 4d1590f to 7ddd54f Compare February 12, 2026 09:56
Luis Silva added 2 commits February 12, 2026 02:03
According to the XARCV 1.8 specification, he arcv.vclr instruction takes
(imm, vl) in the base variant and (vector, imm, vl) for tail-undisturbed.
Test case updated to remove the vector input in base variant, remove mask
intrinsic and add tail-undisturbed.

Signed-off-by: Luis Silva <luiss@synopsys.com>
arcv_vclr clears the lower imm[4:0] number of elements of vd.  However, the
current pattern uses imm5_operand, which only accepts values < 5 and therefore
rejects valid immediates.

The instruction encoding allows a 5-bit unsigned immediate, i.e. values in the
range 0..31.   Introduce a dedicated const_0_31_operand predicate and use it
for arcv_vclr.

Signed-off-by: Luis Silva <luiss@synopsys.com>
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2 participants