cells: rename functional module

[proppy]

Workaround #24

Using:

sed -i -e 's/module \(.*\)(/module \1_func(/' cells/*/*.functional.pp.v

Regenerated the library file with open_pdks https://github.com/RTimothyEdwards/open_pdks/blob/master/common/foundry_install.py:

python3 common/foundry_install.py -source ~/src/github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0/ \
                                  -target /tmp/out \
                                  -library digital gf180mcu_fd_sc_mcu7t5v0 \
                                  -verilog 'cells/*/*.v' compile-only

for testing purpose: gf180mcu_fd_sc_mcu7t5v0.zip

[RTimothyEdwards]

Yes, but the same thing needs to be done for the non-power-pin versions as well.

[urish]

Thanks @proppy!

Still getting some errors, even with the modified file:

/home/uri/p/gf180-game-of-life-cell/test/gf180mcu_fd_sc_mcu7t5v0.v:14585: error: Unknown module type: UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP
2 error(s) during elaboration.
*** These modules were missing:
        UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP referenced 1 times.

[mithro]

@urish - I assume it is related to #27 ?

[urish]

TBH I've no idea - I'm just trying to get to a working gate level simulation of my gf180 submission, and thanks you @proppy slowly figuring it out

[mithro]

@urish - Maybe your test could be added to the repository as a way to verify that the Verilog is working?

[urish]

To which repository, this one?

[mithro]

Maybe? We are making up this as we go.

[urish]

The test is here: https://github.com/urish/gf180-game-of-life-cell/tree/gate-level/test

Right now, it uses @proppy's generated verilog model. If you have cocotb installed, you can run it by checking out the above repo (gate-level branch), and running:

make -C test GATES=yes

Feel free to adopt the test to this repo

[RTimothyEdwards]

@mithro : The answer should be immediately obvious from the report:

*** These modules were missing:
        UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP referenced 1 times.

The primitive added in PR #27 is named gf180mcu_fd_sc_mcu7t5v0__udp_hn_iq_ff, not UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP. So you added the UDP primitives, and changed their names according to your special syntax rules, but didn't bother to fix the places where those UDP primitives are called from other verilog modules.

[urish]

Thanks @RTimothyEdwards. I renamed gf180mcu_fd_sc_mcu7t5v0__udp_hn_iq_ff to UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP, and finally the GL test passes! 🥳

urish/gf180-game-of-life-cell@baf41a8

[antonblanchard]

The primitive added in PR #27 is named gf180mcu_fd_sc_mcu7t5v0__udp_hn_iq_ff, not UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP. So you added the UDP primitives, and changed their names according to your special syntax rules, but didn't bother to fix the places where those UDP primitives are called from other verilog modules.

It looks like all the FF latch and clock gating cells have this issue.