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PR Digest 2026 04 23
Tiotto, Ettore edited this page Apr 23, 2026
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1 revision
Period: 2026-04-13 to 2026-04-23 | Total PRs: 58 (42 from Xe2/Xe3/Xe3P, 16 from Xe4) | Lines changed: +34,139 / -16,040
Major progress on tensor descriptor lowering: descriptor gather and scatter operations now route through efficient hardware 2D block load and store paths, and the backend-side block pointer representation was retired in favor of a Python-only frontend lowering. Correctness work fixed several latent layout, dominance, and arithmetic bugs that could silently produce wrong results in reductions and conditional code. Four upstream synchronizations were completed with test pass rates between 97.77% and 99.55%.
Key accomplishments:
- Unlocked hardware-accelerated 2D block I/O for descriptor gather and scatter, benefiting matrix-heavy AI workloads using the native tensor descriptor API
- Retired the C++ block-pointer representation and associated passes, simplifying the compiler stack by several thousand lines of code
- Fixed multiple correctness bugs in layout remat, dominance tracking, and reduction ordering that produced wrong model outputs
- Introduced a new register-pressure-aware HoistLayoutConversions pass and cleanup passes for loop versioning
- Maintained full alignment with the upstream OpenAI Triton compiler at 97.77%–99.55% pass rates
Lowering improvements for descriptor-based memory access, 1D strided patterns, and the retirement of C++ block-pointer handling in favor of a Python-only frontend path.
- #6730 Implement PredicatedOpInterface on PrefetchOp — Extends PredicatedOpInterface to cover PrefetchOp so predicated prefetch folding can apply. (+7/-0, @etiotto)
- #6739 Revert 1D strided load → 2D block load reshape — Reverts PR #6693 after a regression was found. (+29/-549, @whitneywhtsang)
- #6721 Remove no-mask restriction from blockio — Allows the block_io attribute to be set on masked loads so more ops qualify for 2D block I/O. (+79/-9, @whitneywhtsang)
- #6722 Remove inner tensor type inside tensordesc — Cherry-picks upstream #9851 that removes the redundant inner tensor type from TensorDesc. (+1,517/-1,401, @wdziurdz)
- #6693 1D strided load → 2D block load reshape — Adds a MaterializeBlockPointer rewrite to convert 1D strided loads into 2D block loads (later reverted). (+555/-34, @etiotto)
- #6695 Add H==1 test coverage for 1D strided store reshape — Adds H==1 lit test coverage for the 1D strided store reshape path. (+118/-63, @whitneywhtsang)
- #6691 Refactor 1D strided store into reusable helpers — NFC refactor that extracts 1D strided store transformation logic into shared helpers. (+134/-102, @etiotto)
- #6696 Reland "Rewrite block pointer to be python-only" — Relands upstream #9668 moving all block-pointer handling into the Python frontend. (+97/-625, @whitneywhtsang)
- #6687 Remove remaining Intel block pointer references — NFC cleanup removing stale Intel-specific block-pointer references after the Python migration. (+23/-58, @whitneywhtsang)
- #6682 Restrict 1D strided store reshape to single row tiles — Restricts the 1D strided store reshape transform to single-row tiles to avoid incorrect generation. (+12/-7, @wdziurdz)
- #6676 Remove Intel block pointer handling — Removes the C++ Intel block pointer lowering after the Python-only migration. (+0/-143, @whitneywhtsang)
- #6672 Remove RewriteTensorPointer pass — Retires the RewriteTensorPointer pass now that block pointers are lowered in Python. (+0/-1,508, @whitneywhtsang)
- #6671 Remove BlockPointerToTensorDesc pass — Retires the BlockPointerToTensorDesc pass superseded by the Python frontend lowering. (+0/-638, @whitneywhtsang)
- #6666 Lower block pointers to tensor descriptors in frontend — Moves block-pointer → tensor-descriptor lowering into the Python frontend. (+74/-9, @whitneywhtsang)
- #6655 Conditionally pre-apply alignment in descriptor load lowering — Pre-applies pointer alignment only when the offset is a compile-time constant, reducing runtime arithmetic. (+46/-13, @whitneywhtsang)
- #6604 Rewrite contiguous descriptor_scatter to descriptor_store — Detects contiguous scatter patterns and rewrites them to 2D block stores via descriptor_store. (+402/-105, @etiotto)
- #6584 Rewrite contiguous descriptor_gather to 2D block loads — Detects contiguous gather patterns and rewrites them to 2D block loads. (+568/-45, @etiotto)
Fixes to layout rematerialization, dominance, reduction ordering, and arithmetic UB — each addressing bugs that could produce wrong results in model inference.
- #6460 Add HoistLayoutConversions pass with liveness-based GRF budget heuristic — New pass that hoists layout conversions when estimated live registers fit the GRF budget. (+532/-0, @etiotto)
- #6701 Fix backward remat conflict detection — Corrects conflict detection during backward rematerialization in RemoveLayoutConversions. (+108/-13, @etiotto)
- #6688 Fix dead hoistConvertDotOperand for DPAS encoding — Fixes a dead hoist path so DPAS-encoded dot operands are properly rematerialized. (+70/-2, @etiotto)
- #6497 Workaround reduce-accuracy issue in TIMM (re-port) — Applies the ReduceOp combine-order workaround from #6667 on a second branch. (+954/-15, @whitneywhtsang)
- #6653 Add FoldTrueCmpI and PrepareIfCombining passes to clean up after loop versioning — Adds two TTIR cleanup passes that simplify branches produced by loop versioning. (+698/-2, @etiotto)
- #6667 Workaround reduce-accuracy issue in TIMM models — Preserves the Intel ReduceOp combine order to avoid numerical regression in upstream models. (+951/-15, @chengjunlu)
- #6681 Fix dominance violation in hoistConvertOnTopOfExtOrBroadcast — Fixes a use-before-def created by layout hoisting over extension/broadcast ops. (+88/-13, @wdziurdz)
- #6675 Fix masked div/rem UB exploitation by LLVM O3 — Masks divisor and dividend so O3 cannot exploit UB paths in predicated div/rem. (+120/-93, @etiotto)
4 upstream merges from OpenAI Triton (commits 43badaa, 09a2aad, 4ddb0bd, df82d98) — pass rates 97.77%–99.55%.
Driver and pipeline work: static-launcher migration, CSE tuning, reduce-op refactoring, and the revert of TRITON_INTEL_PREDICATED_LOAD.
- #6718 [ReduceOpToLLVM] Minor changes — Small refactor of ReduceOp-to-LLVM conversion helpers. (+4/-1, @whitneywhtsang)
- #6680 Reorder PyKernelArgType fields to match C++17 declaration order (g++ fix) — Reorders struct fields so g++ compiles the XPU driver without warnings. (+2/-2, @Stonepia)
- #6698 Move tp_dealloc before tp_flags in PyKernelArgType (C++17) — Follow-up field reorder to satisfy C++17 declaration rules. (+1/-1, @Stonepia)
- #6657 Revert "Enable TRITON_INTEL_PREDICATED_LOAD" — Reverts the predicated-load enable after a regression. (+4/-5, @glados-intel)
- #6650 [XPU][DRIVER] Switch to static launcher — Replaces the dynamic kernel launcher with a statically compiled variant. (+865/-450, @anmyachev)
- #6648 Use LoopAwareCSE in make_ttgir to reduce register pressure — Enables the loop-aware CSE variant during TTGIR construction to reduce register pressure. (+2/-1, @etiotto)
CI rebalancing, vLLM patch/workflow simplification, benchmark tooling, and test stability fixes.
- #6731 Remove skipif_is_rocm from vllm_xpu_patch.py — Drops a ROCm-specific patch marker no longer needed for the XPU vLLM flow. (+6/-29, @quinnlp)
- #6726 Fix lit test failures due to non-deterministic operation ordering — Makes FileCheck patterns tolerant of non-deterministic op ordering. (+10/-10, @whitneywhtsang)
- #6716 Skip failing mamba tests (tracked by #6713) — Adds mamba tests to the vLLM skip list pending investigation in #6713. (+10/-0, @quinnlp)
- #6476 Update benchmark CI to install from pre-built wheel artifact — Switches benchmark CI to pre-built wheels to cut install time. (+231/-23, @januszjah)
- #6706 Remove NFC import change from vLLM patch — Removes an unnecessary import churn from the vLLM patch. (+1/-10, @quinnlp)
- #6703 Fix stale swiglu_opts indices in xe2 triton_kernels skiplist — Realigns skiplist indices after upstream test reordering. (+10/-10, @exolyr)
- #6599 Update PyTorch pin — Bumps the PyTorch pin to the latest qualified revision. (+3/-58, @anmyachev)
- #6679 Loosen CPU RAM check in gemm_postop_addmatrix int8 benchmark — Widens the memory threshold so the benchmark does not bail on acceptable RAM. (+6/-4, @whitneywhtsang)
- #6686 Fix BMG workflow and move reports to reusable workflow — Fixes BMG vLLM workflow and centralizes report publishing in a reusable workflow. (+11/-68, @whitneywhtsang)
- #6670 Remove malformed section in vLLM patch — Cleans up a malformed hunk in the vLLM integration patch. (+19/-64, @quinnlp)
- #6678 Use torch sdpa for FlashAttn result check — Switches the FlashAttn benchmark reference to torch SDPA. (+3/-4, @whitneywhtsang)
- #6467 Remove cuda → xpu replacements from vllm-fix.patch — Drops stale CUDA→XPU patch rewrites now handled upstream. (+2/-127, @quinnlp)
- #6617 Move vLLM benchmarks to triton_kernels_benchmark package — Relocates vLLM benchmarks under the shared benchmark package. (+29/-29, @quinnlp)
- #6534 Enable tests from test_debug.py — Enables previously skipped debug-info pytest cases. (+60/-44, @mieshkiwrk)
- #6601 Add vllm-tests bmg workflow — Adds a GitHub Actions workflow running the vLLM test suite on BMG. (+15/-0, @quinnlp)
- #6610 Add fused moe to benchmark — Adds a fused mixture-of-experts kernel benchmark. (+489/-0, @chengjunlu)