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Table-format core register maps
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‎docs/specs/register_map.md‎

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@@ -37,44 +37,35 @@ in that bridge’s section.
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<a id="regmap-ela-user1"></a>
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## ELA core — address map (USER1 control)
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- `0x0000`: `VERSION` (ro) - Core identity and version. `[15:0]` is the
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ASCII core identifier `"LA"` (`0x4C41`, Logic Analyzer); `[23:16]` is
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the minor version; `[31:24]` is the major version. Hosts must verify
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the low-16 magic before trusting any other ELA register on this
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chain. Current value: `0x0002_4C41` (major=0, minor=2, id="LA").
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- `0x0004`: `CTRL` (rw) - Control (arm, reset)
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- `0x0008`: `STATUS` (ro) - Status (armed, triggered, done)
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- `0x000C`: `SAMPLE_W` (ro) - Sample width in bits
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- `0x0010`: `DEPTH` (ro) - Total capture depth in samples
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- `0x0014`: `PRETRIG_LEN` (rw) - Pre-trigger samples
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- `0x0018`: `POSTTRIG_LEN` (rw) - Post-trigger samples
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- `0x001C`: `CAPTURE_LEN` (ro) - Captured sample count for current/last run
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- `0x0020`: `TRIG_MODE` (rw) - Trigger mode
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- `0x0024`: `TRIG_VALUE` (rw) - Compare value
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- `0x0028`: `TRIG_MASK` (rw) - Mask bits
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- `0x002C`: `BURST_PTR` (wo) - Write to initiate burst read from `start_ptr` via USER2.
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`bit[31]` selects the source BRAM: `0` = sample data (default), `1` = timestamp data.
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The host sets `bit[31]=1` when calling `read_timestamp_block()` to burst-read the
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timestamp BRAM through the same USER2 path.
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- `0x0030`: `SQ_MODE` (rw) - Storage qualification mode (0=off, 1=value, 2=edge, 3=both; STOR_QUAL=1 only)
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- `0x0034`: `SQ_VALUE` (rw) - Storage qualification match value
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- `0x0038`: `SQ_MASK` (rw) - Storage qualification match mask
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- `0x00D8`: `STARTUP_ARM` (rw) - Bit 0. When set, RESET leaves the core armed instead of idle. `STARTUP_ARM=1` in RTL changes the power-up default of this register so the bitstream can come up pre-armed immediately after configuration.
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- `0x00DC`: `TRIG_HOLDOFF` (rw) - Trigger holdoff in sample-clock cycles (0..65535). Trigger hits are ignored for N cycles after ARM and after each segmented auto-rearm. Distinct from `TRIG_DELAY`.
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- `0x00D4`: `TRIG_DELAY` (rw) - Post-trigger delay in sample-clock cycles (0..65535). When non-zero, the committed trigger sample is shifted N cycles after the trigger event, compensating for upstream pipeline latency. The pre/post-trigger sample counts and the buffer wrap behavior are unchanged — only the position of the "trigger" anchor moves forward.
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- `0x00E0`: `COMPARE_CAPS` (ro) - Compare capability bitmask. Bits 0-8
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report compare modes implemented by this bitstream. Bit 16 reports
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comparator B / dual-combine support when bit 17 is set. Bit 17 marks the
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extended capability schema; older bitstreams omit bit 17 and should be
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treated as dual-compare capable for compatibility. Default lightweight,
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dual-comparator builds report `0x301C3`; `REL_COMPARE=1` dual-comparator
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builds report `0x301FF`; `DUAL_COMPARE=0` clears bit 16.
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- `0x003C`: `FEATURES` (ro) - Feature flags: `[3:0]`=TRIG_STAGES, `[4]`=STOR_QUAL
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- `0x0040+N*20+0`: `SEQ_STAGE_N_CFG` (rw) - See encoding below
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- `0x0040+N*20+4`: `SEQ_STAGE_N_VALUE_A` (rw) - Comparator A match value
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- `0x0040+N*20+8`: `SEQ_STAGE_N_MASK_A` (rw) - Comparator A mask
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- `0x0040+N*20+12`: `SEQ_STAGE_N_VALUE_B` (rw) - Comparator B match value
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- `0x0040+N*20+16`: `SEQ_STAGE_N_MASK_B` (rw) - Comparator B mask
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| Address | Name | Access | Description |
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|---------|------|--------|-------------|
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| `0x0000` | VERSION | RO | Core identity and version: `[31:24]` major, `[23:16]` minor, `[15:0]` ASCII core ID `"LA"` (`0x4C41`). Hosts verify `VERSION[15:0]` before trusting any other ELA register. Current v0.4 value: `0x0004_4C41`. |
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| `0x0004` | CTRL | RW | Control register; see [CTRL](#regmap-ctrl). |
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| `0x0008` | STATUS | RO | Capture status; see [STATUS](#regmap-status). |
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| `0x000C` | SAMPLE_W | RO | Sample width in bits. |
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| `0x0010` | DEPTH | RO | Total capture depth in samples. |
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| `0x0014` | PRETRIG_LEN | RW | Pre-trigger sample count. |
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| `0x0018` | POSTTRIG_LEN | RW | Post-trigger sample count. |
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| `0x001C` | CAPTURE_LEN | RO | Captured sample count for the current or most recent run. |
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| `0x0020` | TRIG_MODE | RW | Trigger mode; see [TRIG_MODE](#regmap-trig-mode). |
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| `0x0024` | TRIG_VALUE | RW | Trigger comparator value. |
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| `0x0028` | TRIG_MASK | RW | Trigger comparator mask. |
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| `0x002C` | BURST_PTR | WO | Write to initiate burst read from `start_ptr` via USER2. `bit[31]` selects source BRAM: `0` = sample data, `1` = timestamp data. Host timestamp burst readback sets `bit[31]=1`. |
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| `0x0030` | SQ_MODE | RW | Storage qualification mode: 0=off, 1=value, 2=edge, 3=both. Active only when `STOR_QUAL=1`. |
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| `0x0034` | SQ_VALUE | RW | Storage qualification match value. |
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| `0x0038` | SQ_MASK | RW | Storage qualification match mask. |
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| `0x003C` | FEATURES | RO | Feature flags: `[3:0]` = `TRIG_STAGES`, `[4]` = `STOR_QUAL`, other bits report optional build features. |
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| `0x0040 + N*20 + 0` | SEQ_STAGE_N_CFG | RW | Sequencer stage N configuration; see [SEQ_STAGE_N_CFG encoding](#regmap-seq-cfg). |
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| `0x0040 + N*20 + 4` | SEQ_STAGE_N_VALUE_A | RW | Sequencer stage N comparator A match value. |
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| `0x0040 + N*20 + 8` | SEQ_STAGE_N_MASK_A | RW | Sequencer stage N comparator A mask. |
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| `0x0040 + N*20 + 12` | SEQ_STAGE_N_VALUE_B | RW | Sequencer stage N comparator B match value. |
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| `0x0040 + N*20 + 16` | SEQ_STAGE_N_MASK_B | RW | Sequencer stage N comparator B mask. |
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| `0x00D4` | TRIG_DELAY | RW | Post-trigger delay in sample-clock cycles (0..65535). When non-zero, the committed trigger sample shifts N cycles after the trigger event. |
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| `0x00D8` | STARTUP_ARM | RW | Bit 0. When set, RESET leaves the core armed instead of idle. `STARTUP_ARM=1` in RTL changes this register's power-up default. |
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| `0x00DC` | TRIG_HOLDOFF | RW | Trigger holdoff in sample-clock cycles (0..65535). Trigger hits are ignored for N cycles after ARM and after segmented auto-rearm. |
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| `0x00E0` | COMPARE_CAPS | RO | Compare capability bitmask. Bits 0-8 report compare modes. Bit 16 reports comparator B / dual-combine support when bit 17 is set. Bit 17 marks the extended capability schema; older bitstreams omit bit 17 and should be treated as dual-compare capable. |
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| `0x0100 + word*4` | DATA | RO | USER1 sample data window. Present when `USER1_DATA_EN=1`; minimal USER2-only builds may disable this slow fallback window and return zero. |
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<a id="regmap-seq-cfg"></a>
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### SEQ_STAGE_N_CFG encoding
@@ -104,33 +95,34 @@ B-combine sequencer configurations.
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| 6 | RISING | masked bits: all-zero → non-zero |
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| 7 | FALLING | masked bits: non-zero → all-zero |
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| 8 | CHANGED | any masked bit changed from previous sample |
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- `0x0100`: `DATA` window (ro) - Sample data readout (per-word, via USER1).
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Present when `USER1_DATA_EN=1`; minimal USER2-only builds may disable this
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slow fallback window and return zero for these addresses.
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[↑ Top](#regmap-top)
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<a id="regmap-bitfields"></a>
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## Bitfields
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<a id="regmap-version"></a>
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### VERSION
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- [31:24] `major` (8-bit)
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- [23:16] `minor` (8-bit)
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- [15:0] `core_id` — ASCII `"LA"` (`0x4C41`, Logic Analyzer) for the
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fcapz ELA core. Constant per-instance; never zero on a valid
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bitstream. Hosts use this as the core identity check.
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<a id="regmap-ctrl"></a>
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### CTRL
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- [0] `arm` (write 1 to arm)
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- [1] `reset` (write 1 to reset)
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- [31:2] reserved
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<a id="regmap-status"></a>
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### STATUS
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- [0] `armed`
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- [1] `triggered`
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- [2] `done`
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- [3] `overflow`
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- [31:4] reserved
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<a id="regmap-trig-mode"></a>
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### TRIG_MODE
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- [0] `value_match` (1 = compare TRIG_VALUE with mask)
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- [1] `edge_detect` (1 = detect rising edge)
@@ -176,15 +168,16 @@ ELA USER1 and USER2.
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<a id="regmap-eio-addr"></a>
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### Address Map
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- `0x0000`: `VERSION` (ro) — `{major[7:0], minor[7:0], core_id[15:0]}`,
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where `core_id` is ASCII `"IO"` (`0x494F`). Same encoding scheme as the
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ELA core's VERSION at `0x0000`. Hosts must verify the low-16 magic.
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- `0x0004`: `EIO_IN_W` (ro) — Input probe width in bits
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- `0x0008`: `EIO_OUT_W` (ro) — Output probe width in bits
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- `0x0010 + i×4`: `IN[i]` (ro) — probe_in bits [(i+1)×32−1 : i×32], synchronised to jtag_clk via 2-FF
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- `0x0100 + i×4`: `OUT[i]` (rw) — probe_out bits [(i+1)×32−1 : i×32], in jtag_clk domain
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Number of IN words = ⌈IN_W / 32⌉; number of OUT words = ⌈OUT_W / 32⌉.
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| Address | Name | Access | Description |
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|---------|------|--------|-------------|
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| `0x0000` | VERSION | RO | `{major[7:0], minor[7:0], core_id[15:0]}` where `core_id` is ASCII `"IO"` (`0x494F`). Same encoding scheme as ELA VERSION. Hosts verify `VERSION[15:0]`. Current v0.4 value: `0x0004_494F`. |
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| `0x0004` | EIO_IN_W | RO | Input probe width in bits. |
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| `0x0008` | EIO_OUT_W | RO | Output probe width in bits. |
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| `0x0010 + i*4` | IN[i] | RO | `probe_in` bits `[(i+1)*32-1 : i*32]`, synchronized to `jtag_clk` through a 2-FF synchronizer. |
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| `0x0100 + i*4` | OUT[i] | RW | `probe_out` bits `[(i+1)*32-1 : i*32]`, stored in the `jtag_clk` domain. |
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Number of IN words = `ceil(IN_W / 32)`; number of OUT words = `ceil(OUT_W / 32)`.
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<a id="regmap-eio-clk"></a>
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### Clock domains

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