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Add fcapz-web: browser front-end CI #94: Pull request #25 opened by lcapossio
54s feature/web-frontend
feature/web-frontend
54s
Merge pull request #23 from lcapossio/feature/gowin-support CI #93: Commit 96d4b97 pushed by lcapossio
43s main
main
43s
Merge pull request #24 from lcapossio/startup-arm-force-idle CI #92: Commit 92efc27 pushed by lcapossio
42s main
main
42s
Add force_idle() to fix intermittent captures on startup-armed cores CI #91: Pull request #24 synchronize by lcapossio
47s startup-arm-force-idle
startup-arm-force-idle
47s
Add force_idle() to fix intermittent captures on startup-armed cores CI #90: Pull request #24 synchronize by lcapossio
48s startup-arm-force-idle
startup-arm-force-idle
48s
Gowin (BRS-100-GW1NR9) support: EIO reference design, GUI/CLI over OpenOCD, and a hardware test suite CI #89: Pull request #23 opened by lcapossio
41s feature/gowin-support
feature/gowin-support
41s
Merge pull request #22 from lcapossio/docs/slim-readme CI #88: Commit 9ceae26 pushed by lcapossio
38s main
main
38s
Slim README into a beginner-friendly landing page; relocate reference data to the manual CI #87: Pull request #22 opened by lcapossio
42s docs/slim-readme
docs/slim-readme
42s
Merge pull request #21 from lcapossio/vhdl-core-translation CI #86: Commit 92b69f0 pushed by lcapossio
43s main
main
43s
Tighten VHDL parity coverage and trim disabled timestamp RAM CI #85: Pull request #21 opened by lcapossio
44s vhdl-core-translation
vhdl-core-translation
44s
Add GitHub Sponsors funding metadata CI #84: Commit f8b011d pushed by lcapossio
1m 10s main
main
1m 10s
Merge pull request #19 from lcapossio/vhdl-core-translation CI #83: Commit a00e088 pushed by lcapossio
48s main
main
48s
Add VHDL RTL translation and shared cocotb regression CI #82: Pull request #19 synchronize by lcapossio
48s vhdl-core-translation
vhdl-core-translation
48s
Add VHDL RTL translation and shared cocotb regression CI #81: Pull request #19 synchronize by lcapossio
53s vhdl-core-translation
vhdl-core-translation
53s
Add VHDL RTL translation and shared cocotb regression CI #80: Pull request #19 synchronize by lcapossio
49s vhdl-core-translation
vhdl-core-translation
49s
Add VHDL RTL translation and shared cocotb regression CI #79: Pull request #19 synchronize by lcapossio
45s vhdl-core-translation
vhdl-core-translation
45s
Add VHDL RTL translation and shared cocotb regression CI #78: Pull request #19 synchronize by lcapossio
44s vhdl-core-translation
vhdl-core-translation
44s
Add VHDL RTL translation and shared cocotb regression CI #77: Pull request #19 synchronize by lcapossio
49s vhdl-core-translation
vhdl-core-translation
49s
Merge pull request #20 from lcapossio/feature/cocotb-regression CI #76: Commit c26a55b pushed by lcapossio
42s main
main
42s
Add cocotb regression and Verilator ELA coverage runner CI #75: Pull request #20 synchronize by lcapossio
44s feature/cocotb-regression
feature/cocotb-regression
44s
Add cocotb regression and Verilator ELA coverage runner CI #74: Pull request #20 opened by lcapossio
41s feature/cocotb-regression
feature/cocotb-regression
41s
Add BRS-100-GW1NR9 example README CI #73: Commit 3fb028c pushed by lcapossio
45s main
main
45s
Add Brisbane Silicon contributor CI #72: Commit 116e006 pushed by lcapossio
37s main
main
37s
Merge pull request #17 from BrisbaneSilicon/chaywood/pr/brs_100_gw1nr… CI #71: Commit bafe973 pushed by lcapossio
47s main
main
47s
Chaywood/pr/brs 100 gw1nr9 support CI #70: Pull request #17 synchronize by lcapossio
40s BrisbaneSilicon:chaywood/pr/brs_100_gw1nr9_support
BrisbaneSilicon:chaywood/pr/brs_100_gw1nr9_support
40s