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Merge pull request #17 from BrisbaneSilicon/chaywood/pr/brs_100_gw1nr9_support
Chaywood/pr/brs 100 gw1nr9 support
2 parents f4fe4e9 + 4dd12a0 commit bafe973

17 files changed

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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2026 Craig Haywood - BrisbaneSilicon - <support@brisbanesilicon.com.au>
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adapter driver ftdi
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ftdi vid_pid 0x0403 0x6010
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ftdi channel 0
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transport select jtag
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adapter speed 5000
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set _CHIPNAME GW1NR-9C
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set _IDCODE 0x1100481B
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jtag newtap $_CHIPNAME tap -irlen 8 -expected-id $_IDCODE
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init
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2026 Craig Haywood - BrisbaneSilicon - <support@brisbanesilicon.com.au>
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######################### Locations #########################
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IO_LOC "pad_clk_27Mhz" 52;
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IO_LOC "pad_user_buttons_n[0]" 3;
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IO_LOC "pad_user_buttons_n[1]" 4;
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IO_LOC "pad_leds_n[0]" 16;
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IO_LOC "pad_leds_n[1]" 15;
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IO_LOC "pad_leds_n[2]" 14;
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IO_LOC "pad_leds_n[3]" 13;
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IO_LOC "pad_leds_n[4]" 11;
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IO_LOC "pad_leds_n[5]" 10;
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# J5
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IO_LOC "pad_io[1]" 25;
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IO_LOC "pad_io[2]" 26;
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IO_LOC "pad_io[3]" 27;
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IO_LOC "pad_io[4]" 28;
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IO_LOC "pad_io[5]" 29;
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IO_LOC "pad_io[6]" 30;
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IO_LOC "pad_io[7]" 33;
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IO_LOC "pad_io[8]" 34;
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IO_LOC "pad_io[9]" 35;
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IO_LOC "pad_io[10]" 36;
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IO_LOC "pad_io[11]" 37;
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IO_LOC "pad_io[12]" 38;
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IO_LOC "pad_io[13]" 39;
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IO_LOC "pad_io[14]" 40;
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IO_LOC "pad_io[15]" 41;
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IO_LOC "pad_io[16]" 42;
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# J6
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IO_LOC "pad_io[17]" 77;
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IO_LOC "pad_io[18]" 76;
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IO_LOC "pad_io[19]" 75;
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IO_LOC "pad_io[20]" 74;
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IO_LOC "pad_io[21]" 73;
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IO_LOC "pad_io[22]" 72;
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IO_LOC "pad_io[23]" 71;
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IO_LOC "pad_io[24]" 70;
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IO_LOC "pad_io[25]" 69;
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IO_LOC "pad_io[26]" 68;
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IO_LOC "pad_io[27]" 57;
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IO_LOC "pad_io[28]" 56;
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IO_LOC "pad_io[29]" 55;
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IO_LOC "pad_io[30]" 54;
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IO_LOC "pad_io[31]" 53;
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IO_LOC "pad_io[32]" 51;
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######################### Configuration #########################
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IO_PORT "pad_clk_27Mhz" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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IO_PORT "pad_user_buttons_n[0]" PULL_MODE=UP;
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IO_PORT "pad_user_buttons_n[1]" PULL_MODE=UP;
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IO_PORT "pad_leds_n[0]" PULL_MODE=UP DRIVE=8;
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IO_PORT "pad_leds_n[1]" PULL_MODE=UP DRIVE=8;
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IO_PORT "pad_leds_n[2]" PULL_MODE=UP DRIVE=8;
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IO_PORT "pad_leds_n[3]" PULL_MODE=UP DRIVE=8;
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IO_PORT "pad_leds_n[4]" PULL_MODE=UP DRIVE=8;
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IO_PORT "pad_leds_n[5]" PULL_MODE=UP DRIVE=8;
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IO_PORT "pad_io[1]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[2]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[3]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[4]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[5]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[6]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[7]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[8]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[9]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[10]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[11]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[12]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[13]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[14]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[15]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[16]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[17]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[18]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[19]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[20]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[21]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[22]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[23]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[24]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[25]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[26]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[27]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[28]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[29]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[30]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[31]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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IO_PORT "pad_io[32]" IO_TYPE=LVCMOS33 PULL_MODE=DOWN;
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create_clock -name clk_27Mhz -period 37.037 -waveform {0 18.518} [get_ports {pad_clk_27Mhz}]
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create_clock -name clk_60Mhz -period 16.667 -waveform {0 8.335} [get_pins {brs_100_gw1nr9_top/rpll_60mhz_inst/CLKOUT}]
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create_clock -name clk_60Mhz_p -period 16.667 -waveform {0 8.335} [get_pins {brs_100_gw1nr9_top/rpll_60mhz_inst/CLKOUTP}]
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create_clock -name clk_18Mhz -period 55.556 -waveform {0 27.778} [get_pins {brs_100_gw1nr9_top/rpll_18mhz_inst/CLKOUT}]
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create_clock -name clk_18Mhz_p -period 55.556 -waveform {0 27.778} [get_pins {brs_100_gw1nr9_top/rpll_18mhz_inst/CLKOUTP}]
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create_clock -name clk_tck -period 400.000 -waveform {0 200.000} [get_ports {tck_pad_i}]
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# NOTE: all clocks, to/from everything else
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set_false_path -from [get_clocks {clk_27Mhz}] -to [get_clocks {clk_60Mhz}]
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set_false_path -from [get_clocks {clk_60Mhz}] -to [get_clocks {clk_27Mhz}]
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set_false_path -from [get_clocks {clk_27Mhz}] -to [get_clocks {clk_60Mhz_p}]
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set_false_path -from [get_clocks {clk_60Mhz_p}] -to [get_clocks {clk_27Mhz}]
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set_false_path -from [get_clocks {clk_60Mhz}] -to [get_clocks {clk_60Mhz_p}]
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set_false_path -from [get_clocks {clk_60Mhz_p}] -to [get_clocks {clk_60Mhz}]
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set_false_path -from [get_clocks {clk_60Mhz}] -to [get_clocks {clk_tck}]
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set_false_path -from [get_clocks {clk_tck}] -to [get_clocks {clk_60Mhz}]
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set_false_path -from [get_clocks {clk_60Mhz}] -to [get_clocks {clk_18Mhz}]
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set_false_path -from [get_clocks {clk_18Mhz}] -to [get_clocks {clk_60Mhz}]
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set_false_path -from [get_clocks {clk_27Mhz}] -to [get_clocks {clk_18Mhz}]
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set_false_path -from [get_clocks {clk_18Mhz}] -to [get_clocks {clk_27Mhz}]
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set_false_path -from [get_clocks {clk_27Mhz}] -to [get_clocks {clk_18Mhz_p}]
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set_false_path -from [get_clocks {clk_18Mhz_p}] -to [get_clocks {clk_27Mhz}]
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set_false_path -from [get_clocks {clk_18Mhz}] -to [get_clocks {clk_18Mhz_p}]
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set_false_path -from [get_clocks {clk_18Mhz_p}] -to [get_clocks {clk_18Mhz}]
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set_false_path -from [get_clocks {clk_18Mhz}] -to [get_clocks {clk_tck}]
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set_false_path -from [get_clocks {clk_tck}] -to [get_clocks {clk_18Mhz}]
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set_false_path -from [get_clocks {clk_27Mhz}] -to [get_clocks {clk_tck}]
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set_false_path -from [get_clocks {clk_tck}] -to [get_clocks {clk_27Mhz}]

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