terasic_de10nano: Add Cyclone V HPS (cyclonev_hps) CPU support

[enjoy-digital]

Companion PR to enjoy-digital/litex#2496 (Intel Cyclone V HPS hardcore CPU support).

Allow building the DE10-Nano/MiSTer SoC with --cpu-type=cyclonev_hps:

• The HPS becomes the SoC's CPU through the H2F LW bridge (CSRs at 0xff20_0000).
• LiteX UART disabled (console is on HPS UART0, running Linux on MiSTer).
• sram/rom regions mapped to HPS DDR3 (Linker-only, enables BIOS compilation as on Zynq targets).
• The MiSTer SDRAM (when enabled) is made visible to the ARM at 0xc000_0000 through the H2F bridge (also exposed via --with-h2f-bridge).
• --with-f2h-sdram: first 256MB of HPS DDR3 exposed on the LiteX bus at 0xd000_0000 through F2SDRAM Port 1 (64-bit Avalon-MM) and the new Wishbone2AvalonMM bridge — useful for Fabric DMAs and as a F2SDRAM smoke test from the ARM (reading 0xd000_0000 from the HPS returns the DDR3 content at 0x0000_0000).
• MiSTer build/load/test instructions documented at the top of the target.

The softcore path is unchanged.

Tested: full Quartus 23.1 builds (with and without --with-f2h-sdram): 0 errors, .rbf produced, HPS bridge/F2SDRAM atoms placed/routed; BIOS compiled with arm-none-eabi-gcc. Hardware bring-up on a MiSTer is the next step:

./terasic_de10nano.py --cpu-type=cyclonev_hps --with-mister-sdram --with-f2h-sdram --build
scp build/terasic_de10nano/gateware/terasic_de10nano.rbf root@<mister-ip>:/media/fat/litex.rbf
ssh root@<mister-ip> "echo load_core /media/fat/litex.rbf > /dev/MiSTer_cmd"
ssh root@<mister-ip> "devmem 0xff200004" # ctrl_scratch -> 0x12345678
ssh root@<mister-ip> "devmem 0xd0000000" # HPS DDR3 @ 0x0 through F2SDRAM