cpu/cyclonev_hps: Add Intel Cyclone V HPS (hard dual Cortex-A9) support

[enjoy-digital]

This PR adds Intel Cyclone V HPS support as a hardcore CPU (--cpu-type=cyclonev_hps), similar to what is already done for Zynq7000/ZynqMP, targeting boards where the HPS is pre-booted from SD-Card (e.g. MiSTer/DE10-Nano) and where only the Fabric-side bridge interfaces are then required.

Integration:

• H2F LW AXI3 master used as the LiteX peripheral bus, with the bridge's window-relative addresses extended to ARM physical addresses so that the LiteX memory map matches the ARM's view (CSRs at 0xff20_0000, directly usable from the HPS with devmem//dev/mem).
• Optional H2F AXI3 master (0xc000_0000, 960MB window) via add_axi_h2f_master() and F2H AXI3 slave via add_axi_f2h_slave() for Fabric -> HPS DDR3/peripherals accesses.
• F2SDRAM Avalon-MM ports via add_fpga2sdram_port() for direct (higher bandwidth) Fabric -> HPS SDRAM Controller accesses; the port layout is fixed (Port 0: 128-bit, Ports 1/2: 64-bit) to match the configuration applied by MiSTer's Preloader/U-Boot.
• F2H interrupts (32 IRQs) and Clocks/Resets/Trace/Boot tie-offs.
• New generic interconnect/avalon Wishbone2AvalonMM bridge (with simulation coverage) to connect the F2SDRAM Avalon-MM ports to the LiteX bus.
• BIOS/software support files (UART redirected to HPS UART0/16550, configured by the Preloader/U-Boot); the BIOS is only compiled when the target adds rom/sram regions in HPS DDR3, as on Zynq targets.
• GIC-aware BIOS interrupt support for bare-metal use (BIOS launched from U-Boot with go 0x01000000): Cortex-A9 crt0.S with exception vectors at the image start (VBAR), VFP enable, IRQ-mode stack and AAPCS IRQ trampoline; GIC-390 irq.h (the 32-bit LiteX interrupt mask maps to the F2H IRQs / GIC IDs 72-103 without disturbing other IDs); IAR/EOIR claim-based ISR dispatch in libbase/isr.c.

Implementation notes:

• The HPS is integrated through direct cyclonev_hps_interface_* atom instantiation (no Qsys/Platform Designer). Port lists were taken from Quartus's WYSIWYG component library and cross-checked against MiSTer's sys framework (which instantiates the same atoms directly); the F2SDRAM atom configuration/wiring replicates MiSTer's generated sys framework.
• Unused H2F/F2H bridges are explicitly instantiated with port_size_config=unused, as done by MiSTer; the F2SDRAM atom is only instantiated when at least one port is used.
• The dbg_apb tie-off atom used by MiSTer (Quartus 17) is not instantiated: it is no longer present in recent Quartus releases (23.1) and is not required.

Tested:

• Full Quartus 23.1 builds on the DE10-Nano target (see companion litex-boards PR), with and without F2SDRAM: 0 errors, bridges/F2SDRAM atoms placed/routed, .rbf produced; BIOS compiles with arm-none-eabi-gcc.
• Wishbone2AvalonMM simulation test (32/64-bit, base address translation, wait-states, pipelined read latency).
• GIC/crt0 path verified by building the BIOS with arm-none-eabi-gcc and inspecting the disassembly: vectors at rom base/entry point (0x01000000), GIC Distributor/CPU Interface accesses (ITARGETSR/PMR/CTLRs) inlined in main() through irq_setie(1), exception return sequence — runtime behavior still to be validated on hardware.
• Softcore DE10-Nano path unchanged/still elaborates.
• Hardware bring-up on a MiSTer is the next step (CSR access from HPS Linux with devmem, SDRAM access at 0xc000_0000 through the H2F bridge, HPS DDR3 access at 0xd000_0000 through F2SDRAM).

Companion PRs: litex-hub/litex-boards#746 (DE10-Nano target), #2497 (litex_server --devmem for remote litex_cli/litescope accesses from the HPS).

Possible follow-ups: Qsys backend for standalone (non pre-booted) boards.