targets/radiona_ulx4m_ld_v2: Disable DDR3 DM - #774
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…void build failure due to dm pads not in the same group than others
enjoy-digital
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Updated this PR for the finalized LiteDRAM #401 API. Commit f8915d3 replaces dm_skip with with_dm=False and fixes the constructor alignment; commit 624d811 rejects l2_size=0 because disabling DM requires full-width writes. Validation against LiteDRAM #401: the radiona_ulx4m_ld_v2 no-compile target build passes, the zero-cache configuration fails with the intended diagnostic, and all 14 fast lint/parser tests pass. The boards CI is running; its build remains dependent on #401 being available from LiteDRAM master. |
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Thanks @trabucayre! |
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ULX4M-LD routes its DDR3 DM pins outside the DQS groups, so the ECP5 DDR output primitive cannot drive them. This uses with_dm=False from enjoy-digital/litedram#401 to hold DM low. Since masked writes are unavailable, the target requires a non-zero L2 cache so memory writes remain full-width. Depends on enjoy-digital/litedram#401.