[FIRRTL] Support probe ports in instance_choice operations

include/circt/Dialect/FIRRTL/FIRRTLUtils.h

@@ -74,6 +74,22 @@ class TieOffCache {
   SmallDenseMap<Type, Value, 8> cache;
 };
 
+// Instance choice option case macro name utilities.
+class InstanceChoiceMacroTable {
+public:
+  InstanceChoiceMacroTable(Operation *op);
+
+  // Get the macro for an option case. Return null if it doesn't exist.
+  FlatSymbolRefAttr getMacro(StringAttr optionName, StringAttr caseName) const;
+
+  // Get all option/case pairs in the IR occurrence order.
+  auto getKeys() const { return cache.keys(); }
+
+private:
+  // Option/Case -> Macro Symbol
+  llvm::MapVector<std::pair<StringAttr, StringAttr>, FlatSymbolRefAttr> cache;
+};
+
 //===----------------------------------------------------------------------===//
 // Template utilities
 //===----------------------------------------------------------------------===//

integration_test/Dialect/FIRRTL/instance-choice.fir

@@ -0,0 +1,70 @@
+; REQUIRES: verilator
+; This test verifies that the instance choice header inclusion mechanism works correctly
+; with probes to access internal signals:
+
+; RUN: rm -rf %t && mkdir -p %t
+; RUN: firtool %s --split-verilog -o=%t
+; Check it errors when including both headers.
+; RUN: not verilator %t/targets_top_Platform_ASIC.svh %t/targets_top_Platform_FPGA.svh %t/top.sv %t/ASICTarget.sv %t/FPGATarget.sv %t/DefaultTarget.sv --lint-only --top-module top 2>&1 | FileCheck %s --check-prefix=ERROR
+; RUN: verilator %driver %t/targets_top_Platform_ASIC.svh %t/top.sv %t/ASICTarget.sv %t/FPGATarget.sv %t/DefaultTarget.sv %t/ref_top.sv --cc --sv --exe --build -o %t.asic.exe --top-module top
+; RUN: %t.asic.exe --cycles 1 2>&1 | FileCheck %s --check-prefix=ASIC
+; RUN: verilator %driver %t/targets_top_Platform_FPGA.svh %t/top.sv %t/ASICTarget.sv %t/FPGATarget.sv %t/DefaultTarget.sv %t/ref_top.sv --cc --sv --exe --build -o %t.fpga.exe --top-module top
+; RUN: %t.fpga.exe --cycles 1 2>&1 | FileCheck %s --check-prefix=FPGA
+; RUN: verilator %driver %t/top.sv %t/ASICTarget.sv %t/FPGATarget.sv %t/DefaultTarget.sv %t/ref_top.sv --cc --sv --exe --build -o %t.default.exe --top-module top
+; RUN: %t.default.exe --cycles 1 2>&1 | FileCheck %s --check-prefix=DEFAULT
+;
+; ERROR: must__not__be__set
+;
+; ASIC: result:         10
+; ASIC: internal:       15
+; FPGA: result:         20
+; FPGA: internal:       25
+; DEFAULT: result:       0
+; DEFAULT: internal:      5
+
+FIRRTL version 5.1.0
+circuit top:
+  option Platform:
+    FPGA
+    ASIC
+
+  module DefaultTarget:
+    output result: UInt<32>
+    output internal_probe: Probe<UInt<32>>
+
+    wire internal: UInt<32>
+    connect internal, UInt<32>(5)
+    connect result, UInt<32>(0)
+    define internal_probe = probe(internal)
+
+  module ASICTarget:
+    output result: UInt<32>
+    output internal_probe: Probe<UInt<32>>
+
+    wire internal: UInt<32>
+    connect internal, UInt<32>(15)
+    connect result, UInt<32>(10)
+    define internal_probe = probe(internal)
+
+  module FPGATarget:
+    output result: UInt<32>
+    output internal_probe: Probe<UInt<32>>
+
+    wire internal: UInt<32>
+    connect internal, UInt<32>(25)
+    connect result, UInt<32>(20)
+    define internal_probe = probe(internal)
+
+  public module top:
+    input clk: Clock
+    input rst: UInt<1>
+
+    instchoice proc of DefaultTarget, Platform:
+      ASIC => ASICTarget
+      FPGA => FPGATarget
+
+    wire probed_value: UInt<32>
+    connect probed_value, read(proc.internal_probe)
+
+    printf(clk, UInt<1>(1), "result: %d\n", proc.result)
+    printf(clk, UInt<1>(1), "internal: %d\n", probed_value)