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[ImportVerilog] Fix moore.conversion legalization failure on interface ports #9927

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[ImportVerilog] Fix moore.conversion legalization failure on interface ports #9927

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4 changes: 2 additions & 2 deletions lib/Conversion/ImportVerilog/Structure.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -568,8 +568,8 @@ struct ModuleVisitor : public BaseVisitor {
outputValues.push_back(val);
} else {
// For input ports, if the value is a ref (from VariableOp/NetOp),
// read it to get the rvalue.
if (isa<moore::RefType>(val.getType()))
// read it to get the rvalue, unless the port itself expects a ref.
if (isa<moore::RefType>(val.getType()) && !isa<moore::RefType>(fp.type))
val = moore::ReadOp::create(builder, loc, val);
inputValues.push_back(val);
}
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23 changes: 22 additions & 1 deletion test/Conversion/ImportVerilog/basic.sv
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Expand Up @@ -4789,4 +4789,25 @@ module TopTwoPorts;
IfaceModport i1();
IfaceModport i2();
TwoPortsSameType dut(.a(i1), .b(i2));
endmodule
endmodule

// The test from sv-test
interface test_bus;
logic test_pad;
endinterface: test_bus

// CHECK-LABEL: moore.module private @sub(in %iface_test_pad : !moore.ref<l1>) {
// CHECK: moore.output
// CHECK: }
module sub(test_bus iface);
endmodule

// CHECK-LABEL: moore.module @top() {
// CHECK: %iface_test_pad = moore.variable : <l1>
// CHECK: moore.instance "sub" @sub(iface_test_pad: %iface_test_pad: !moore.ref<l1>) -> ()
// CHECK: moore.output
// CHECK: }
module top;
test_bus iface();
sub sub (.iface);
endmodule
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