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[SV] Switch passes to ODS constructors, NFC #9929

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[SV] Switch passes to ODS constructors, NFC #9929

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10 changes: 0 additions & 10 deletions include/circt/Dialect/SV/SVPasses.h
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Original file line number Diff line number Diff line change
Expand Up @@ -14,23 +14,13 @@
#define CIRCT_DIALECT_SV_SVPASSES_H

#include "mlir/Pass/Pass.h"
#include "llvm/ADT/StringRef.h"

namespace circt {
namespace sv {

#define GEN_PASS_DECL
#include "circt/Dialect/SV/SVPasses.h.inc"

std::unique_ptr<mlir::Pass> createPrettifyVerilogPass();
std::unique_ptr<mlir::Pass> createHWCleanupPass(bool mergeAlwaysBlocks = true);
std::unique_ptr<mlir::Pass> createHWStubExternalModulesPass();
std::unique_ptr<mlir::Pass> createHWLegalizeModulesPass();
std::unique_ptr<mlir::Pass> createSVTraceIVerilogPass();
std::unique_ptr<mlir::Pass> createHWGeneratorCalloutPass();
std::unique_ptr<mlir::Pass> createHWEliminateInOutPortsPass(
const HWEliminateInOutPortsOptions &options = {});
std::unique_ptr<mlir::Pass> createHWExportModuleHierarchyPass();
/// Generate the code for registering passes.
#define GEN_PASS_REGISTRATION
#include "circt/Dialect/SV/SVPasses.h.inc"
Expand Down
9 changes: 0 additions & 9 deletions include/circt/Dialect/SV/SVPasses.td
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Expand Up @@ -29,7 +29,6 @@ def HWCleanup : Pass<"hw-cleanup", "hw::HWModuleOp"> {
"true", "Allow always and always_ff blocks to be merged">
];

let constructor = "circt::sv::createHWCleanupPass()";
}

def HWLegalizeModules : Pass<"hw-legalize-modules", "hw::HWModuleOp"> {
Expand All @@ -42,7 +41,6 @@ def HWLegalizeModules : Pass<"hw-legalize-modules", "hw::HWModuleOp"> {
constructs.
}];

let constructor = "circt::sv::createHWLegalizeModulesPass()";
}

def PrettifyVerilog : Pass<"prettify-verilog", "hw::HWModuleOp"> {
Expand All @@ -55,7 +53,6 @@ def PrettifyVerilog : Pass<"prettify-verilog", "hw::HWModuleOp"> {
it is self contained.
}];

let constructor = "circt::sv::createPrettifyVerilogPass()";
}

def HWStubExternalModules : Pass<"hw-stub-external-modules",
Expand All @@ -66,7 +63,6 @@ def HWStubExternalModules : Pass<"hw-stub-external-modules",
useful for linting to eliminate missing file errors.
}];

let constructor = "circt::sv::createHWStubExternalModulesPass()";
let dependentDialects = ["circt::sv::SVDialect"];
}

Expand All @@ -76,8 +72,6 @@ def HWGeneratorCalloutPass : Pass<"hw-generator-callout", "ModuleOp"> {
This pass calls an external program for all the hw.module.generated nodes,
following the description in the hw.generator.schema node.
}];
let constructor = "circt::sv::createHWGeneratorCalloutPass()";

let options = [
Option<"schemaName", "schema-name", "std::string",
"", "Name of the schema to process">,
Expand All @@ -95,7 +89,6 @@ def SVTraceIVerilog : Pass<"sv-trace-iverilog", "ModuleOp"> {
tracing in an iverilog simulation.
}];

let constructor = "circt::sv::createSVTraceIVerilogPass()";
let dependentDialects = ["circt::sv::SVDialect"];
let options = [
Option<"topOnly", "top-only", "bool", "true",
Expand All @@ -116,7 +109,6 @@ def HWExportModuleHierarchy : Pass<"hw-export-module-hierarchy",
sv.verbatim ops with the output_file attribute.
}];

let constructor = "circt::sv::createHWExportModuleHierarchyPass()";
let dependentDialects = ["circt::emit::EmitDialect", "circt::sv::SVDialect"];
}

Expand All @@ -129,7 +121,6 @@ def HWEliminateInOutPorts : Pass<"hw-eliminate-inout-ports",
input and output ports at the using module, and subsequently moving the
inout read- and writes to the instantiation site.
}];
let constructor = "circt::sv::createHWEliminateInOutPortsPass()";
let dependentDialects = ["circt::sv::SVDialect"];
let options = [
Option<"readSuffix", "read-suffix", "std::string", "\"_rd\"",
Expand Down
5 changes: 1 addition & 4 deletions lib/Dialect/SV/Transforms/GeneratorCallout.cpp
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Expand Up @@ -40,6 +40,7 @@ namespace {
struct HWGeneratorCalloutPass
: public circt::sv::impl::HWGeneratorCalloutPassBase<
HWGeneratorCalloutPass> {
using Base::Base;
void runOnOperation() override;

void processGenerator(HWModuleGeneratedOp generatedModuleOp,
Expand Down Expand Up @@ -168,7 +169,3 @@ void HWGeneratorCalloutPass::processGenerator(
extMod->setAttr("filenames", builder.getStringAttr(fileContent));
generatedModuleOp.erase();
}

std::unique_ptr<Pass> circt::sv::createHWGeneratorCalloutPass() {
return std::make_unique<HWGeneratorCalloutPass>();
}
7 changes: 1 addition & 6 deletions lib/Dialect/SV/Transforms/HWCleanup.cpp
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Expand Up @@ -101,6 +101,7 @@ static void mergeRegions(Region *region1, Region *region2) {

namespace {
struct HWCleanupPass : public circt::sv::impl::HWCleanupBase<HWCleanupPass> {
using Base::Base;
using sv::impl::HWCleanupBase<HWCleanupPass>::mergeAlwaysBlocks;

void runOnOperation() override;
Expand Down Expand Up @@ -248,9 +249,3 @@ void HWCleanupPass::runOnProceduralRegion(Region &region) {
runOnRegionsInOp(op);
}
}

std::unique_ptr<Pass> circt::sv::createHWCleanupPass(bool mergeAlwaysBlocks) {
auto pass = std::make_unique<HWCleanupPass>();
pass->mergeAlwaysBlocks = mergeAlwaysBlocks;
return pass;
}
5 changes: 0 additions & 5 deletions lib/Dialect/SV/Transforms/HWEliminateInOutPorts.cpp
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Expand Up @@ -233,8 +233,3 @@ void HWEliminateInOutPortsPass::runOnOperation() {
}
}
}

std::unique_ptr<Pass> circt::sv::createHWEliminateInOutPortsPass(
const HWEliminateInOutPortsOptions &options) {
return std::make_unique<HWEliminateInOutPortsPass>(options);
}
8 changes: 0 additions & 8 deletions lib/Dialect/SV/Transforms/HWExportModuleHierarchy.cpp
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Expand Up @@ -143,11 +143,3 @@ void HWExportModuleHierarchyPass::runOnOperation() {

markAllAnalysesPreserved();
}

//===----------------------------------------------------------------------===//
// Pass Creation
//===----------------------------------------------------------------------===//

std::unique_ptr<mlir::Pass> sv::createHWExportModuleHierarchyPass() {
return std::make_unique<HWExportModuleHierarchyPass>();
}
4 changes: 0 additions & 4 deletions lib/Dialect/SV/Transforms/HWLegalizeModules.cpp
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Expand Up @@ -478,7 +478,3 @@ void HWLegalizeModulesPass::runOnOperation() {
if (!anythingChanged)
markAllAnalysesPreserved();
}

std::unique_ptr<Pass> circt::sv::createHWLegalizeModulesPass() {
return std::make_unique<HWLegalizeModulesPass>();
}
4 changes: 0 additions & 4 deletions lib/Dialect/SV/Transforms/HWStubExternalModules.cpp
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Expand Up @@ -61,7 +61,3 @@ void HWStubExternalModulesPass::runOnOperation() {
module.erase();
}
}

std::unique_ptr<Pass> circt::sv::createHWStubExternalModulesPass() {
return std::make_unique<HWStubExternalModulesPass>();
}
4 changes: 0 additions & 4 deletions lib/Dialect/SV/Transforms/PrettifyVerilog.cpp
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Expand Up @@ -578,7 +578,3 @@ void PrettifyVerilogPass::runOnOperation() {
if (!anythingChanged)
markAllAnalysesPreserved();
}

std::unique_ptr<Pass> circt::sv::createPrettifyVerilogPass() {
return std::make_unique<PrettifyVerilogPass>();
}
5 changes: 1 addition & 4 deletions lib/Dialect/SV/Transforms/SVTraceIVerilog.cpp
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Expand Up @@ -39,6 +39,7 @@ namespace {

struct SVTraceIVerilogPass
: public circt::sv::impl::SVTraceIVerilogBase<SVTraceIVerilogPass> {
using Base::Base;
void runOnOperation() override;
};

Expand Down Expand Up @@ -77,7 +78,3 @@ void SVTraceIVerilogPass::runOnOperation() {
sv::VerbatimOp::create(builder, hwmod.getLoc(), ss.str());
}
}

std::unique_ptr<Pass> circt::sv::createSVTraceIVerilogPass() {
return std::make_unique<SVTraceIVerilogPass>();
}
10 changes: 5 additions & 5 deletions lib/Firtool/Firtool.cpp
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Expand Up @@ -357,8 +357,8 @@ LogicalResult firtool::populateHWToSV(mlir::PassManager &pm,
modulePM.addPass(mlir::createCSEPass());
modulePM.addPass(createSimpleCanonicalizerPass());
modulePM.addPass(mlir::createCSEPass());
modulePM.addPass(sv::createHWCleanupPass(
/*mergeAlwaysBlocks=*/!opt.shouldEmitSeparateAlwaysBlocks()));
modulePM.addPass(sv::createHWCleanup(
{/*mergeAlwaysBlocks=*/!opt.shouldEmitSeparateAlwaysBlocks()}));
}

// Check inner symbols and inner refs.
Expand All @@ -379,11 +379,11 @@ populatePrepareForExportVerilog(mlir::PassManager &pm,
pm.addNestedPass<hw::HWModuleOp>(verif::createVerifyClockedAssertLikePass());

// Legalize unsupported operations within the modules.
pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModulesPass());
pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModules());

// Tidy up the IR to improve verilog emission quality.
if (!opt.shouldDisableOptimization())
pm.nest<hw::HWModuleOp>().addPass(sv::createPrettifyVerilogPass());
pm.nest<hw::HWModuleOp>().addPass(sv::createPrettifyVerilog());

if (opt.shouldStripFirDebugInfo())
pm.addPass(circt::createStripDebugInfoWithPredPass([](mlir::Location loc) {
Expand All @@ -398,7 +398,7 @@ populatePrepareForExportVerilog(mlir::PassManager &pm,

// Emit module and testbench hierarchy JSON files.
if (opt.shouldExportModuleHierarchy())
pm.addPass(sv::createHWExportModuleHierarchyPass());
pm.addPass(sv::createHWExportModuleHierarchy());

// Check inner symbols and inner refs.
pm.addPass(hw::createVerifyInnerRefNamespace());
Expand Down
8 changes: 4 additions & 4 deletions tools/hlstool/hlstool.cpp
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Expand Up @@ -291,15 +291,15 @@ static void loadHWLoweringPipeline(OpPassManager &pm) {
pm.nest<hw::HWModuleOp>().addPass(circt::seq::createLowerSeqHLMem());
pm.addPass(seq::createHWMemSimImpl());
pm.addPass(circt::createLowerSeqToSVPass());
pm.nest<hw::HWModuleOp>().addPass(sv::createHWCleanupPass());
pm.nest<hw::HWModuleOp>().addPass(sv::createHWCleanup());

// Legalize unsupported operations within the modules.
pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModulesPass());
pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModules());
pm.addPass(createSimpleCanonicalizerPass());

// Tidy up the IR to improve verilog emission quality.
auto &modulePM = pm.nest<hw::HWModuleOp>();
modulePM.addPass(sv::createPrettifyVerilogPass());
modulePM.addPass(sv::createPrettifyVerilog());
}

// --------------------------------------------------------------------------
Expand Down Expand Up @@ -367,7 +367,7 @@ static LogicalResult doHLSFlowDynamic(
addIRLevel(IRLevel::SV, [&]() { loadHWLoweringPipeline(pm); });

if (traceIVerilog)
pm.addPass(circt::sv::createSVTraceIVerilogPass());
pm.addPass(circt::sv::createSVTraceIVerilog());

if (loweringOptions.getNumOccurrences())
loweringOptions.setAsAttribute(module);
Expand Down
8 changes: 4 additions & 4 deletions tools/kanagawatool/kanagawatool.cpp
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Expand Up @@ -197,18 +197,18 @@ static void loadHWLoweringPipeline(OpPassManager &pm) {
pm.nest<hw::HWModuleOp>().addPass(circt::seq::createLowerSeqHLMem());
pm.addPass(seq::createHWMemSimImpl());
pm.addPass(circt::createLowerSeqToSVPass());
pm.nest<hw::HWModuleOp>().addPass(sv::createHWCleanupPass());
pm.nest<hw::HWModuleOp>().addPass(sv::createHWCleanup());
pm.addPass(mlir::createCSEPass());
pm.addPass(circt::comb::createLowerComb());
pm.nest<hw::HWModuleOp>().addPass(circt::createLowerHWToSVPass());

// Legalize unsupported operations within the modules.
pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModulesPass());
pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModules());
pm.addPass(createSimpleCanonicalizerPass());

// Tidy up the IR to improve verilog emission quality.
auto &modulePM = pm.nest<hw::HWModuleOp>();
modulePM.addPass(sv::createPrettifyVerilogPass());
modulePM.addPass(sv::createPrettifyVerilog());
}

static void loadSchedulingPipeline(OpPassManager &pm) {
Expand Down Expand Up @@ -253,7 +253,7 @@ static void loadLowLevelPassPipeline(
loadESILoweringPipeline(pm);
loadHWLoweringPipeline(pm);
if (traceIVerilog)
pm.addPass(circt::sv::createSVTraceIVerilogPass());
pm.addPass(circt::sv::createSVTraceIVerilog());

if (loweringOptions.getNumOccurrences())
loweringOptions.setAsAttribute(module);
Expand Down
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