firtool-1.146.0

What's Changed

• [ci] Use old (macOS) bash-compatible lowercase by @seldridge in #10306
• [circt-test] Print empty JSON array when listing tests on empty input by @ankit-cybertron in #10295
• [AGENTs] Fix ESI/PyCDE directions and add a style rule by @teqdruid in #10307
• [ESI][Runtime] Switch ReadChannelPort to segmented by @teqdruid in #10308
• [ci] Exclude z3 from macOS tests by @seldridge in #10309
• [CI] Add extra_cmake_args option to UBTI and enable LLVM_ENABLE_REVERSE_ITERATION by @uenoku in #10300
• [lldh] Revert Recent Mem2Reg Changes by @seldridge in #10318
• [Synth][FunctionalReduction] Add a newVar interface to SATSolver and use it in FR by @okekayode in #10316
• [Synth] Add dot gate by @uenoku in #10277
• Bump LLVM by @uenoku in #10320
• [CI] Enable Reverse iteration by @uenoku in #10312
• [Synth][FunctionalReduction] Improve choice materialization with reachability of choice by @okekayode in #10319
• [SimToSV] support lowering stdout/stderr by @nanjo712 in #10283
• [OM] Switch to IntegerBinaryInterface by @seldridge in #10328
• [Synth][FunctionalReduction] Remove redundant reachable values from choice classes by @okekayode in #10325
• [Support][SATSolver] Add at-most-one / exactly-one clause helpers by @uenoku in #10324
• [FIRRTL][OM] Add Bool/Integer And/Or/Xor by @seldridge in #10322
• [LowerToHW] Extract the logic related to file descriptor acquisition as a common utility function by @nanjo712 in #10288
• [FSM] Canonicalize away no-op updates by @TaoBi22 in #10336
• Prioritize in-tree MLIR headers in unified builds by @gipsyh in #10331
• [Synth] Clean up boolean logic interface, NFC by @uenoku in #10333
• [OM] Add ElaboratedObjectOp by @uenoku in #10334
• [ESI][Runtime] Fix race condition in port disconnects by @teqdruid in #10342
• [ESI][Runtime] Refactor promise fulfill logic in ReadChannelPort by @teqdruid in #10343
• [ESI][Runtime] TypeDeserializer handles complex messages by @teqdruid in #10310
• Bump LLVM to 90c90a41bed5ba2e4c7b724ecfd533f6f3f7d204 by @TaoBi22 in #10345
• [CoreToFSM] Avoid violating pattern invariants in getReachableStates by @TaoBi22 in #10347
• [MSFT] Fix Python DeviceDB test by @teqdruid in #10351
• [OM] Clean up ObjectOfieldOp: Move away from symbols, remove a field path and VerifyObjectFields pass by @uenoku in #10303
• [OM] Drop memory effects from Class, Object by @seldridge in #10352
• [FSMToSMT] Allow fsm.machines with no outputs/vars by @TaoBi22 in #10354
• [FIRRTL] InferDomains: On error, print more diagnostic information by @rwy7 in #10337
• [CoreToFSM] Move topological sorts to avoid pattern invariant violation by @TaoBi22 in #10355
• [ExportVerilog] Drop 'reg' for unpacked arrays too by @teqdruid in #10361
• [FIRRTL] Add "hasProperties" to InstanceInfo by @seldridge in #10359
• [NFC][FSMToSMT] Make error test names more informative by @TaoBi22 in #10364
• [CellIFT] Add CellIFT instrumentation pass for HW/Comb/Seq IR by @flaviens in #10250
• [SimToSV] lower sim.get_file to i32 fd by @nanjo712 in #10335
• [FIRRTL] Include "public" in hasProperties logic by @seldridge in #10365
• [LLHD] Run Mem2Reg per slot to fix cubic scaling by @fabianschuiki in #10321
• [LLHD][Deseq] Lower reset-only async reset processes as register holds by @gipsyh in #10344
• [Moore][ImportVerilog] Implement static $cast via materializeConversion by @sunhailong2001 in #10156
• [CI] Run integration tests in Clang as well by @uenoku in #10366
• [ESI][Runtime] Update AGENTS.md with debuging tips by @teqdruid in #10367
• [ESI][Runtime] Message translation: check for support by @teqdruid in #10368
• [PyCDE] Modules to convert parallel <--> serial lists by @teqdruid in #10360
• [PyCDE] Add AGENTS.md with hardware dev tips by @teqdruid in #10369
• [FIRRTL] Create classes for transitive properties by @seldridge in #10362

New Contributors

• @gipsyh made their first contribution in #10331
• @flaviens made their first contribution in #10250

Full Changelog: firtool-1.145.0...firtool-1.146.0