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Issues list

[SystemZ] Handle f16 load positive/negative/complement without libcalls. backend:SystemZ
#136286 opened Apr 18, 2025 by JonPsson1 Loading…
1
[SystemZ] Add DAGCombine for FCOPYSIGN to remove rounding. backend:SystemZ
#136131 opened Apr 17, 2025 by JonPsson1 Loading…
3
[SystemZ] Add proper mcount handling backend:SystemZ llvm:transforms
#135767 opened Apr 15, 2025 by dominik-steenken Loading…
4
[CostModel] Remove optional from InstructionCost::getValue() backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 function-specialization llvm:analysis llvm:support llvm:transforms vectorizers
#135596 opened Apr 14, 2025 by davemgreen Loading…
6
[release/20.x] Support z17 processor name and scheduler description backend:SystemZ clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:analysis mc Machine (object) code
#135413 opened Apr 11, 2025 by uweigand Loading… LLVM 20.X Release
3
[SystemZ][TTI]Wrong costs for insertelement with even/odd indices backend:SystemZ
#135346 opened Apr 11, 2025 by alexey-bataev
8
[SystemZ] Add a SystemZ specific pre-RA scheduling strategy. backend:SystemZ llvm:codegen
#135076 opened Apr 9, 2025 by JonPsson1 Loading…
13
[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector backend:PowerPC backend:SystemZ backend:WebAssembly backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#135010 opened Apr 9, 2025 by rohitaggarwal007 Loading…
7
[SystemZ] Large compile time regression in SystemZTTIImpl::adjustInliningThreshold() backend:SystemZ slow-compile
#134714 opened Apr 7, 2025 by alexrp LLVM 20.X Release
@JonPsson1
13
[GOFF] Add writing of section symbols backend:SystemZ llvm:binary-utilities mc Machine (object) code
#133799 opened Mar 31, 2025 by redstar Loading…
@redstar
121
[GlobalIsel] Avoid aligning alloca size. backend:AArch64 backend:PowerPC backend:SystemZ backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#132064 opened Mar 19, 2025 by jcogan-nv Loading…
14
[PHIElimination] Reuse existing COPY in predecessor basic block backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:SystemZ backend:X86 debuginfo llvm:globalisel llvm:regalloc llvm:transforms
#131837 opened Mar 18, 2025 by guy-david Loading…
6
[MachineCopyProp, SystemZ] "Using an undefined physical register" backend:SystemZ llvm:codegen
#131478 opened Mar 15, 2025 by JonPsson1
11
[CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM backend:AArch64 backend:AMDGPU backend:SystemZ backend:X86 debuginfo llvm:codegen
#129690 opened Mar 4, 2025 by vikramRH Loading…
6
s390x: support .machine push and .machine pop assembler directives backend:SystemZ enhancement Improving things as opposed to bug fixing, e.g. new or missing feature
#129053 opened Feb 27, 2025 by folkertdev
1
[VectorCombine] Shrink loads used in shufflevector rebroadcasts backend:SystemZ clang Clang issues not falling into any other category llvm:transforms vectorizers
#128938 opened Feb 26, 2025 by PeddleSpam Loading…
24
[Support] report_fatal_error: Do not generate crash backtrace by default backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:SystemZ backend:WebAssembly backend:X86 debuginfo llvm:binary-utilities llvm:globalisel llvm:support llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO) mc Machine (object) code
#128495 opened Feb 24, 2025 by optimisan • Draft
19
[HLSL] Use hlsl_device address space for getpointer. backend:AArch64 backend:AMDGPU backend:DirectX backend:SystemZ backend:WebAssembly clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category HLSL HLSL Language Support
#127675 opened Feb 18, 2025 by s-perron Loading…
1
15
Add support for flag output operand "=@cc" for SystemZ. backend:AArch64 backend:SystemZ clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:SelectionDAG SelectionDAGISel as well
#125970 opened Feb 6, 2025 by anoopkg6 Loading…
41
[clang][CodeGen][AA] Add !llvm.errno.tbaa gathering int-compatible TBAA nodes backend:AMDGPU backend:SystemZ clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis llvm:instcombine llvm:transforms
#125258 opened Jan 31, 2025 by antoniofrighetto Loading…
7
[Clang] [NFC] Rename isAnyPointerType() and getPointeeOrArrayElementType(). backend:AArch64 backend:ARM backend:RISC-V backend:SystemZ clang:analysis clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang:static analyzer clang Clang issues not falling into any other category clang-tidy clang-tools-extra clangd HLSL HLSL Language Support lldb
#122938 opened Jan 14, 2025 by Sirraide Loading…
12
[IR] Don't set strictfp on irrelevant calls backend:AMDGPU backend:SystemZ backend:X86 clang Clang issues not falling into any other category floating-point Floating-point math llvm:ir llvm:support llvm:transforms
#122735 opened Jan 13, 2025 by spavloff Loading…
@spavloff
22
[MachineLICM] Recognize registers clobbered at EH landing pad entry backend:SystemZ llvm:codegen miscompilation
#122446 opened Jan 10, 2025 by uweigand Loading…
1
6
[IR][AsmParser] Revamp how floating-point literals work in LLVM IR. backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:loongarch backend:NVPTX backend:PowerPC backend:RISC-V backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category debuginfo HLSL HLSL Language Support llvm:adt llvm:analysis llvm:globalisel llvm:instcombine llvm:ir llvm:support llvm:transforms
#121838 opened Jan 6, 2025 by jcranmer-intel Loading…
28
[SystemZ] Bad machine code: Illegal virtual register for instruction backend:SystemZ llvm:regalloc
#121232 opened Dec 27, 2024 by JonPsson1
1
ProTip! What’s not been updated in a month: updated:<2025-03-20.