[release/20.x] Support z17 processor name and scheduler description #135413
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The recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15. This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson. Manual backport of llvm#135254
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@llvm/pr-subscribers-clang-driver @llvm/pr-subscribers-clang Author: Ulrich Weigand (uweigand) ChangesThe recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15. This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson. Manual backport of #135254 Patch is 151.11 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/135413.diff 59 Files Affected:
diff --git a/clang/lib/Basic/Targets/SystemZ.cpp b/clang/lib/Basic/Targets/SystemZ.cpp
index c836d110d26d5..6326188b3bd18 100644
--- a/clang/lib/Basic/Targets/SystemZ.cpp
+++ b/clang/lib/Basic/Targets/SystemZ.cpp
@@ -105,7 +105,7 @@ static constexpr ISANameRevision ISARevisions[] = {
{{"arch12"}, 12}, {{"z14"}, 12},
{{"arch13"}, 13}, {{"z15"}, 13},
{{"arch14"}, 14}, {{"z16"}, 14},
- {{"arch15"}, 15},
+ {{"arch15"}, 15}, {{"z17"}, 15},
};
int SystemZTargetInfo::getISARevision(StringRef Name) const {
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c b/clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c
index 5b4051c8d6f17..717a7d7ab49e2 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c
@@ -1,6 +1,6 @@
// REQUIRES: systemz-registered-target
-// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm -x c++ %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm -x c++ %s -o - | FileCheck %s
unsigned long test_bdepg(unsigned long a, unsigned long b) {
// CHECK-LABEL: test_bdepg
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c b/clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c
index 3943a15af9d2f..8275b9ddb88a8 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c
@@ -1,5 +1,5 @@
// REQUIRES: systemz-registered-target
-// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-unknown-unknown \
+// RUN: %clang_cc1 -target-cpu z17 -triple s390x-unknown-unknown \
// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s
typedef __attribute__((vector_size(16))) signed char vec_schar;
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c b/clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c
index c3621819e71f9..b765fa64b33d4 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c
@@ -1,5 +1,5 @@
// REQUIRES: systemz-registered-target
-// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -flax-vector-conversions=none \
+// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
typedef __attribute__((vector_size(16))) signed char vec_schar;
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c
index 9f4844efd6312..79041b923068e 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c
@@ -1,5 +1,5 @@
// REQUIRES: systemz-registered-target
-// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
+// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
// RUN: -fzvector -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
index 7a29dbf552e0b..6ee9e1ee3a117 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
@@ -1,8 +1,8 @@
// REQUIRES: systemz-registered-target
-// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
+// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
// RUN: -O2 -fzvector -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
+// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
// RUN: -O2 -fzvector -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -S %s -o - | FileCheck %s --check-prefix=CHECK-ASM
diff --git a/clang/test/CodeGen/SystemZ/systemz-abi-vector.c b/clang/test/CodeGen/SystemZ/systemz-abi-vector.c
index 1e1926678ec33..e5704709a3a33 100644
--- a/clang/test/CodeGen/SystemZ/systemz-abi-vector.c
+++ b/clang/test/CodeGen/SystemZ/systemz-abi-vector.c
@@ -18,6 +18,8 @@
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
+// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu z17 \
+// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
diff --git a/clang/test/CodeGen/SystemZ/systemz-abi.c b/clang/test/CodeGen/SystemZ/systemz-abi.c
index 58081bdc6cc2a..7de425950e9fd 100644
--- a/clang/test/CodeGen/SystemZ/systemz-abi.c
+++ b/clang/test/CodeGen/SystemZ/systemz-abi.c
@@ -24,6 +24,8 @@
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: -emit-llvm -o - %s -mfloat-abi soft | FileCheck %s \
// RUN: --check-prefixes=CHECK,SOFT-FLOAT
+// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu z17 \
+// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
diff --git a/clang/test/Driver/systemz-march.c b/clang/test/Driver/systemz-march.c
index 93a11c6c9c013..8922db9f2d5d6 100644
--- a/clang/test/Driver/systemz-march.c
+++ b/clang/test/Driver/systemz-march.c
@@ -15,6 +15,7 @@
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch13 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH13 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=z16 %s 2>&1 | FileCheck --check-prefix=CHECK-Z16 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch14 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH14 %s
+// RUN: %clang -target s390x -### -S -emit-llvm -march=z17 %s 2>&1 | FileCheck --check-prefix=CHECK-Z17 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch15 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH15 %s
// CHECK-Z9: error: unknown target CPU 'z9'
@@ -32,6 +33,7 @@
// CHECK-ARCH13: "-target-cpu" "arch13"
// CHECK-Z16: "-target-cpu" "z16"
// CHECK-ARCH14: "-target-cpu" "arch14"
+// CHECK-Z17: "-target-cpu" "z17"
// CHECK-ARCH15: "-target-cpu" "arch15"
int x;
diff --git a/clang/test/Misc/target-invalid-cpu-note/systemz.c b/clang/test/Misc/target-invalid-cpu-note/systemz.c
index b70173f5feec2..021c280d53190 100644
--- a/clang/test/Misc/target-invalid-cpu-note/systemz.c
+++ b/clang/test/Misc/target-invalid-cpu-note/systemz.c
@@ -20,4 +20,5 @@
// CHECK-SAME: {{^}}, arch14
// CHECK-SAME: {{^}}, z16
// CHECK-SAME: {{^}}, arch15
+// CHECK-SAME: {{^}}, z17
// CHECK-SAME: {{$}}
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index f267f1759cdb5..2d17891071aae 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -4394,6 +4394,9 @@
// RUN: %clang -march=arch15 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH15
+// RUN: %clang -march=z17 -E -dM %s -o - 2>&1 \
+// RUN: -target s390x-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH15
// CHECK_SYSTEMZ_ARCH15: #define __ARCH__ 15
// CHECK_SYSTEMZ_ARCH15: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SYSTEMZ_ARCH15: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 2b8269e440e90..049865c81667a 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -254,7 +254,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ROTR, MVT::i128, Expand);
setOperationAction(ISD::ROTL, MVT::i128, Expand);
- // No special instructions for these before arch15.
+ // No special instructions for these before z17.
if (!Subtarget.hasVectorEnhancements3()) {
setOperationAction(ISD::MUL, MVT::i128, Expand);
setOperationAction(ISD::MULHS, MVT::i128, Expand);
@@ -281,7 +281,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
// Use VPOPCT and add up partial results.
setOperationAction(ISD::CTPOP, MVT::i128, Custom);
- // Additional instructions available with arch15.
+ // Additional instructions available with z17.
if (Subtarget.hasVectorEnhancements3()) {
setOperationAction(ISD::ABS, MVT::i128, Legal);
}
@@ -353,7 +353,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
setOperationAction(ISD::CTLZ, MVT::i64, Legal);
- // On arch15 we have native support for a 64-bit CTTZ.
+ // On z17 we have native support for a 64-bit CTTZ.
if (Subtarget.hasMiscellaneousExtensions4()) {
setOperationAction(ISD::CTTZ, MVT::i32, Promote);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Promote);
@@ -4466,7 +4466,7 @@ SDValue SystemZTargetLowering::lowerMULH(SDValue Op,
SDLoc DL(Op);
SDValue Even, Odd;
- // This custom expander is only used on arch15 and later for 64-bit types.
+ // This custom expander is only used on z17 and later for 64-bit types.
assert(!is32Bit(VT));
assert(Subtarget.hasMiscellaneousExtensions2());
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrVector.td b/llvm/lib/Target/SystemZ/SystemZInstrVector.td
index edd20a5de8c63..a4ece32c79d88 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrVector.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrVector.td
@@ -1973,7 +1973,7 @@ let Predicates = [FeatureVector] in {
(VLEG (VGBM 0), bdxaddr12only:$addr, 1)>;
}
-// In-register i128 sign-extensions on arch15.
+// In-register i128 sign-extensions on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (sext_inreg VR128:$x, i8)), (VUPLG (VSEGB VR128:$x))>;
def : Pat<(i128 (sext_inreg VR128:$x, i16)), (VUPLG (VSEGH VR128:$x))>;
@@ -1993,7 +1993,7 @@ let Predicates = [FeatureVector] in {
(VSRAB (VREPG VR128:$x, 1), (VREPIB 64))>;
}
-// Sign-extensions from GPR to i128 on arch15.
+// Sign-extensions from GPR to i128 on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (sext_inreg (anyext GR32:$x), i8)),
(VUPLG (VLVGP (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32)),
diff --git a/llvm/lib/Target/SystemZ/SystemZProcessors.td b/llvm/lib/Target/SystemZ/SystemZProcessors.td
index 75b6671dc7723..0827701a48b5a 100644
--- a/llvm/lib/Target/SystemZ/SystemZProcessors.td
+++ b/llvm/lib/Target/SystemZ/SystemZProcessors.td
@@ -41,4 +41,5 @@ def : ProcessorModel<"z15", Z15Model, Arch13SupportedFeatures.List>;
def : ProcessorModel<"arch14", Z16Model, Arch14SupportedFeatures.List>;
def : ProcessorModel<"z16", Z16Model, Arch14SupportedFeatures.List>;
-def : ProcessorModel<"arch15", Z16Model, Arch15SupportedFeatures.List>;
+def : ProcessorModel<"arch15", Z17Model, Arch15SupportedFeatures.List>;
+def : ProcessorModel<"z17", Z17Model, Arch15SupportedFeatures.List>;
diff --git a/llvm/lib/Target/SystemZ/SystemZSchedule.td b/llvm/lib/Target/SystemZ/SystemZSchedule.td
index d683cc042e5c9..cc03a71d8a649 100644
--- a/llvm/lib/Target/SystemZ/SystemZSchedule.td
+++ b/llvm/lib/Target/SystemZ/SystemZSchedule.td
@@ -60,6 +60,7 @@ def VBU : SchedWrite; // Virtual branching unit
def MCD : SchedWrite; // Millicode
+include "SystemZScheduleZ17.td"
include "SystemZScheduleZ16.td"
include "SystemZScheduleZ15.td"
include "SystemZScheduleZ14.td"
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index 2c01691707cc3..a9354ea76c72c 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -1555,12 +1555,12 @@ def : InstRW<[WLat2, VecDFX, NormalGr], (instregex "V(T|C)P$")>;
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VSCH(S|D|X)?P$")>;
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VSCSHP$")>;
-def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VCSPH")>;
-def : InstRW<[WLat2, WLat2, VecXsPm, NormalGr], (instregex "VCLZDP")>;
-def : InstRW<[WLat10, WLat10, VecDF2, NormalGr], (instregex "VSRPR")>;
-def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VPKZR")>;
-def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZH")>;
-def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZL")>;
+def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VCSPH$")>;
+def : InstRW<[WLat2, WLat2, VecXsPm, NormalGr], (instregex "VCLZDP$")>;
+def : InstRW<[WLat10, WLat10, VecDF2, NormalGr], (instregex "VSRPR$")>;
+def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VPKZR$")>;
+def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZH$")>;
+def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZL$")>;
// -------------------------------- System ---------------------------------- //
@@ -1597,8 +1597,8 @@ def : InstRW<[WLat30, MCD], (instregex "S(T)?PX$")>;
// System: Breaking-Event-Address-Register Instructions
//===----------------------------------------------------------------------===//
-def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LBEAR")>;
-def : InstRW<[WLat1, LSU2, FXb, GroupAlone], (instregex "STBEAR")>;
+def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LBEAR$")>;
+def : InstRW<[WLat1, LSU2, FXb, GroupAlone], (instregex "STBEAR$")>;
//===----------------------------------------------------------------------===//
// System: Storage-Key and Real Memory Instructions
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ17.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ17.td
new file mode 100644
index 0000000000000..bd52627f636a7
--- /dev/null
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ17.td
@@ -0,0 +1,1754 @@
+//--- SystemZScheduleZ17.td - SystemZ Scheduling Definitions ---*- tblgen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for Z17 to support instruction
+// scheduling and other instruction cost heuristics.
+//
+// Pseudos expanded right after isel do not need to be modelled here.
+//
+//===----------------------------------------------------------------------===//
+
+def Z17Model : SchedMachineModel {
+
+ let UnsupportedFeatures = Arch15UnsupportedFeatures.List;
+
+ let IssueWidth = 6; // Number of instructions decoded per cycle.
+ let MicroOpBufferSize = 60; // Issue queues
+ let LoadLatency = 1; // Optimistic load latency.
+
+ let PostRAScheduler = 1;
+
+ // Extra cycles for a mispredicted branch.
+ let MispredictPenalty = 20;
+}
+
+let SchedModel = Z17Model in {
+// These definitions need the SchedModel value. They could be put in a
+// subtarget common include file, but it seems the include system in Tablegen
+// currently (2016) rejects multiple includes of same file.
+
+// Decoder grouping rules
+let NumMicroOps = 1 in {
+ def : WriteRes<NormalGr, []>;
+ def : WriteRes<BeginGroup, []> { let BeginGroup = 1; }
+ def : WriteRes<EndGroup, []> { let EndGroup = 1; }
+}
+def : WriteRes<Cracked, []> {
+ let NumMicroOps = 2;
+ let BeginGroup = 1;
+}
+def : WriteRes<GroupAlone, []> {
+ let NumMicroOps = 3;
+ let BeginGroup = 1;
+ let EndGroup = 1;
+}
+def : WriteRes<GroupAlone2, []> {
+ let NumMicroOps = 6;
+ let BeginGroup = 1;
+ let EndGroup = 1;
+}
+def : WriteRes<GroupAlone3, []> {
+ let NumMicroOps = 9;
+ let BeginGroup = 1;
+ let EndGroup = 1;
+}
+
+// Incoming latency removed from the register operand which is used together
+// with a memory operand by the instruction.
+def : ReadAdvance<RegReadAdv, 4>;
+
+// LoadLatency (above) is not used for instructions in this file. This is
+// instead the role of LSULatency, which is the latency value added to the
+// result of loads and instructions with folded memory operands.
+def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
+
+let NumMicroOps = 0 in {
+ foreach L = 1-30 in
+ def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
+}
+
+// Execution units.
+def Z17_FXaUnit : ProcResource<2>;
+def Z17_FXbUnit : ProcResource<2>;
+def Z17_LSUnit : ProcResource<2>;
+def Z17_VecUnit : ProcResource<2>;
+def Z17_VecFPdUnit : ProcResource<2> { let BufferSize = 1; /* blocking */ }
+def Z17_VBUnit : ProcResource<2>;
+def Z17_MCD : ProcResource<1>;
+
+// Subtarget specific definitions of scheduling resources.
+let NumMicroOps = 0 in {
+ def : WriteRes<FXa, [Z17_FXaUnit]>;
+ def : WriteRes<FXb, [Z17_FXbUnit]>;
+ def : WriteRes<LSU, [Z17_LSUnit]>;
+ def : WriteRes<VecBF, [Z17_VecUnit]>;
+ def : WriteRes<VecDF, [Z17_VecUnit]>;
+ def : WriteRes<VecDFX, [Z17_VecUnit]>;
+ def : WriteRes<VecMul, [Z17_VecUnit]>;
+ def : WriteRes<VecStr, [Z17_VecUnit]>;
+ def : WriteRes<VecXsPm, [Z17_VecUnit]>;
+ foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
+ def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z17_FXaUnit]>;
+ def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z17_FXbUnit]>;
+ def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z17_LSUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z17_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z17_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z17_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z17_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z17_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z17_VecUnit]>;
+ }}
+
+ def : WriteRes<VecFPd, [Z17_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
+ def : WriteRes<VecFPd20, [Z17_VecFPdUnit]> { let ReleaseAtCycles = [20]; }
+
+ def : WriteRes<VBU, [Z17_VBUnit]>; // Virtual Branching Unit
+}
+
+def : WriteRes<MCD, [Z17_MCD]> { let NumMicroOps = 3;
+ let BeginGroup = 1;
+ let EndGroup = 1; }
+
+// -------------------------- INSTRUCTIONS ---------------------------------- //
+
+// InstRW constructs have been used in order to preserve the
+// readability of the InstrInfo files.
+
+// For each instruction, as matched by a regexp, provide a list of
+// resources that it needs. These will be combined into a SchedClass.
+
+//===----------------------------------------------------------------------===//
+// Stack allocation
+//===----------------------------------------------------------------------===//
+
+// Pseudo -> LA / LAY
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "ADJDYNALLOC$")>;
+
+//===----------------------------------------------------------------------===//
+// Branch instructions
+//===----------------------------------------------------------------------===//
+
+// Branch
+def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
+def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?J(G)?(Asm.*)?$")>;
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;
+def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
+def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
+def : InstRW<[WLat1, FXa...
[truncated]
|
uweigand
changed the title
|
This is a pretty large patch, how safe is this? |
A lot of this are test and comment-only changes, which should be harmless. Beyond that, the only actual changes are
In order of priority, I'd really like to get the "z17" name in; the scheduler description would be good; the rest is just clean-up to keep the sources in line with mainline. |
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The recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15.
This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson.
Manual backport of #135254