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[SelectionDAG] Improve value type selection for inline asm within selected register class #135097

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[SelectionDAG] Improve value type selection for inline asm within selected register class #135097

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42a0aff
patch
dlee992 Apr 9, 2025
72f7612
update tests for NVPTX
dlee992 Apr 9, 2025
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15 changes: 13 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9738,16 +9738,27 @@ getRegistersForValue(SelectionDAG &DAG, const SDLoc &DL,
// register class, find it.
unsigned AssignedReg;
const TargetRegisterClass *RC;
const MVT RefValueVT = RefOpInfo.ConstraintVT;
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Keep using ConstraintVT directly?

std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint(
&TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT);
&TRI, RefOpInfo.ConstraintCode, RefValueVT);
// RC is unset only on failure. Return immediately.
if (!RC)
return std::nullopt;

// Get the actual register value type. This is important, because the user
// may have asked for (e.g.) the AX register in i32 type. We need to
// remember that AX is actually i16 to get the right extension.
const MVT RegVT = *TRI.legalclasstypes_begin(*RC);
MVT RegVT = *TRI.legalclasstypes_begin(*RC);

// If the reference value type is legal and belongs to the register class,
// use it instead of the first legal value type. This avoids generating
// inaccurate load/store instructions or unnecessary type extensions and
// truncations.
if (TLI.isTypeLegal(RefValueVT) &&
llvm::is_contained(llvm::make_range(TRI.legalclasstypes_begin(*RC),
TRI.legalclasstypes_end(*RC)),
RefValueVT.SimpleTy))
Comment on lines +9758 to +9760
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This is reinventing RC->isTypeLegalForClass. It should also be redundant to check isTypeLegal. I'd assume this looks something like

if (!isTypeLegalForClass()) 
  RegVT = *TRI.legalclasstypes_begin(*RC)

RegVT = RefValueVT.SimpleTy;

if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) {
// If this is an FP operand in an integer register (or visa versa), or more
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17 changes: 17 additions & 0 deletions llvm/test/CodeGen/NVPTX/bf16-instructions.ll
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Expand Up @@ -81,6 +81,23 @@ define bfloat @test_fadd(bfloat %0, bfloat %1) {
ret bfloat %3
}

define bfloat @test_fadd_inlineasm(bfloat %0, bfloat %1) nounwind {
; SM90-LABEL: test_fadd_inlineasm(
; SM90: {
; SM90-NEXT: .reg .b16 %rs<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
; SM90-NEXT: ld.param.b16 %rs2, [test_fadd_inlineasm_param_0];
; SM90-NEXT: ld.param.b16 %rs3, [test_fadd_inlineasm_param_1];
; SM90-NEXT: // begin inline asm
; SM90-NEXT: add.rn.bf16 %rs1, %rs2, %rs3
; SM90-NEXT: // end inline asm
; SM90-NEXT: st.param.b16 [func_retval0], %rs1;
; SM90-NEXT: ret;
%3 = tail call bfloat asm "add.rn.bf16 $0, $1, $2", "=h,h,h"(bfloat %0, bfloat %1) nounwind
ret bfloat %3
}

define bfloat @test_fsub(bfloat %0, bfloat %1) {
; SM70-LABEL: test_fsub(
; SM70: {
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