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[InstCombine] Combine and->cmp->sel->or-disjoint into and->mul #135274

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[InstCombine] Combine and->cmp->sel->or-disjoint into and->mul #135274

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79ebe27
[InstCombine] Combine and->cmp->sel->or-disjoint into and->mul
jrbyrnes Apr 9, 2025
eacb0d8
Address review comments
jrbyrnes Apr 14, 2025
107ec00
Review comments 2
jrbyrnes Apr 15, 2025
06aa825
Remove unused variables
jrbyrnes Apr 15, 2025
e435cd1
Review comments 3
jrbyrnes Apr 15, 2025
5d7f583
Support mismatched preds + move tests
jrbyrnes Apr 16, 2025
a811795
Require the NE side to be non-zero
jrbyrnes Apr 17, 2025
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Formatting
jrbyrnes Apr 17, 2025
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42 changes: 42 additions & 0 deletions llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3643,6 +3643,48 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
foldAddLikeCommutative(I.getOperand(1), I.getOperand(0),
/*NSW=*/true, /*NUW=*/true))
return R;

Value *Cond0 = nullptr, *Cond1 = nullptr;
ConstantInt *Op0True = nullptr, *Op0False = nullptr;
ConstantInt *Op1True = nullptr, *Op1False = nullptr;

// (!(A & N) ? 0 : N * C) + (!(A & M) ? 0 : M * C) -> A & (N + M) * C
if (match(I.getOperand(0), m_Select(m_Value(Cond0), m_ConstantInt(Op0True),
m_ConstantInt(Op0False))) &&
match(I.getOperand(1), m_Select(m_Value(Cond1), m_ConstantInt(Op1True),
m_ConstantInt(Op1False))) &&
Op0True->isZero() && Op1True->isZero() &&
Op0False->getValue().tryZExtValue() &&
Op1False->getValue().tryZExtValue()) {
CmpPredicate Pred0, Pred1;
Value *CmpOp0 = nullptr, *CmpOp1 = nullptr;
ConstantInt *Op0Cond = nullptr, *Op1Cond = nullptr;
if (match(Cond0,
m_c_ICmp(Pred0, m_Value(CmpOp0), m_ConstantInt(Op0Cond))) &&
match(Cond1,
m_c_ICmp(Pred1, m_Value(CmpOp1), m_ConstantInt(Op1Cond))) &&
Pred0 == ICmpInst::ICMP_EQ && Pred1 == ICmpInst::ICMP_EQ &&
Op0Cond->isZero() && Op1Cond->isZero()) {
Value *AndSrc0 = nullptr, *AndSrc1 = nullptr;
ConstantInt *BitSel0 = nullptr, *BitSel1 = nullptr;
if (match(CmpOp0, m_And(m_Value(AndSrc0), m_ConstantInt(BitSel0))) &&
match(CmpOp1, m_And(m_Value(AndSrc1), m_ConstantInt(BitSel1))) &&
AndSrc0 == AndSrc1 && BitSel0->getValue().tryZExtValue() &&
BitSel1->getValue().tryZExtValue()) {
unsigned Out0 = Op0False->getValue().getZExtValue();
unsigned Out1 = Op1False->getValue().getZExtValue();
unsigned Sel0 = BitSel0->getValue().getZExtValue();
unsigned Sel1 = BitSel1->getValue().getZExtValue();
if (!(Out0 % Sel0) && !(Out1 % Sel1) &&
((Out0 / Sel0) == (Out1 / Sel1))) {
auto NewAnd = Builder.CreateAnd(
AndSrc0, ConstantInt::get(AndSrc0->getType(), Sel0 + Sel1));
return BinaryOperator::CreateMul(
NewAnd, ConstantInt::get(NewAnd->getType(), (Out1 / Sel1)));
}
}
}
}
}

Value *X, *Y;
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114 changes: 110 additions & 4 deletions llvm/test/Transforms/InstCombine/or.ll
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Expand Up @@ -1281,10 +1281,10 @@ define <16 x i1> @test51(<16 x i1> %arg, <16 x i1> %arg1) {
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i1> [[ARG:%.*]], <16 x i1> [[ARG1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 23, i32 24, i32 9, i32 10, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: ret <16 x i1> [[TMP3]]
;
%tmp = and <16 x i1> %arg, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>
%tmp2 = and <16 x i1> %arg1, <i1 false, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true>
%tmp3 = or <16 x i1> %tmp, %tmp2
ret <16 x i1> %tmp3
%temp = and <16 x i1> %arg, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>
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To silence a update_test_checks warning

%temp2 = and <16 x i1> %arg1, <i1 false, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true>
%temp3 = or <16 x i1> %temp, %temp2
ret <16 x i1> %temp3
}

; This would infinite loop because it reaches a transform
Expand Down Expand Up @@ -2035,3 +2035,109 @@ define i32 @or_xor_and_commuted3(i32 %x, i32 %y, i32 %z) {
%or1 = or i32 %xor, %yy
ret i32 %or1
}

define i32 @add_select_cmp_and1(i32 %in) {
; CHECK-LABEL: @add_select_cmp_and1(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
; CHECK-NEXT: ret i32 [[OUT]]
;
%bitop0 = and i32 %in, 1
%cmp0 = icmp eq i32 %bitop0, 0
%bitop1 = and i32 %in, 2
%cmp1 = icmp eq i32 %bitop1, 0
%sel0 = select i1 %cmp0, i32 0, i32 72
%sel1 = select i1 %cmp1, i32 0, i32 144
%out = or disjoint i32 %sel0, %sel1
ret i32 %out
}

define i32 @add_select_cmp_and2(i32 %in) {
; CHECK-LABEL: @add_select_cmp_and2(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 5
; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
; CHECK-NEXT: ret i32 [[OUT]]
;
%bitop0 = and i32 %in, 1
%cmp0 = icmp eq i32 %bitop0, 0
%bitop1 = and i32 %in, 4
%cmp1 = icmp eq i32 %bitop1, 0
%sel0 = select i1 %cmp0, i32 0, i32 72
%sel1 = select i1 %cmp1, i32 0, i32 288
%out = or disjoint i32 %sel0, %sel1
ret i32 %out
}

define i32 @add_select_cmp_and3(i32 %in) {
; CHECK-LABEL: @add_select_cmp_and3(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
; CHECK-NEXT: [[TEMP:%.*]] = mul nuw nsw i32 [[TMP1]], 72
; CHECK-NEXT: [[BITOP2:%.*]] = and i32 [[IN]], 4
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[BITOP2]], 0
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i32 0, i32 288
; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[TEMP]], [[SEL2]]
; CHECK-NEXT: ret i32 [[OUT]]
;
%bitop0 = and i32 %in, 1
%cmp0 = icmp eq i32 %bitop0, 0
%bitop1 = and i32 %in, 2
%cmp1 = icmp eq i32 %bitop1, 0
%sel0 = select i1 %cmp0, i32 0, i32 72
%sel1 = select i1 %cmp1, i32 0, i32 144
%temp = or disjoint i32 %sel0, %sel1
%bitop2 = and i32 %in, 4
%cmp2 = icmp eq i32 %bitop2, 0
%sel2 = select i1 %cmp2, i32 0, i32 288
%out = or disjoint i32 %temp, %sel2
ret i32 %out
}

define i32 @add_select_cmp_and4(i32 %in) {
; CHECK-LABEL: @add_select_cmp_and4(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
; CHECK-NEXT: [[TEMP:%.*]] = mul nuw nsw i32 [[TMP1]], 72
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[IN]], 12
; CHECK-NEXT: [[TEMP2:%.*]] = mul nuw nsw i32 [[TMP2]], 72
; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[TEMP]], [[TEMP2]]
; CHECK-NEXT: ret i32 [[OUT]]
;
%bitop0 = and i32 %in, 1
%cmp0 = icmp eq i32 %bitop0, 0
%bitop1 = and i32 %in, 2
%cmp1 = icmp eq i32 %bitop1, 0
%sel0 = select i1 %cmp0, i32 0, i32 72
%sel1 = select i1 %cmp1, i32 0, i32 144
%temp = or disjoint i32 %sel0, %sel1
%bitop2 = and i32 %in, 4
%cmp2 = icmp eq i32 %bitop2, 0
%bitop3 = and i32 %in, 8
%cmp3 = icmp eq i32 %bitop3, 0
%sel2 = select i1 %cmp2, i32 0, i32 288
%sel3 = select i1 %cmp3, i32 0, i32 576
%temp2 = or disjoint i32 %sel2, %sel3
%out = or disjoint i32 %temp, %temp2
ret i32 %out
}



define i32 @add_select_cmp_and_mismatch(i32 %in) {
; CHECK-LABEL: @add_select_cmp_and_mismatch(
; CHECK-NEXT: [[BITOP0:%.*]] = and i32 [[IN:%.*]], 1
; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[BITOP0]], 0
; CHECK-NEXT: [[BITOP1:%.*]] = and i32 [[IN]], 3
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[BITOP1]], 0
; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 0, i32 72
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 0, i32 288
; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
; CHECK-NEXT: ret i32 [[OUT]]
;
%bitop0 = and i32 %in, 1
%cmp0 = icmp eq i32 %bitop0, 0
%bitop1 = and i32 %in, 3
%cmp1 = icmp eq i32 %bitop1, 0
%sel0 = select i1 %cmp0, i32 0, i32 72
%sel1 = select i1 %cmp1, i32 0, i32 288
%out = or disjoint i32 %sel0, %sel1
ret i32 %out
}