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release/20.x: [LoongArch] Don't crash on instruction prefetch intrinsics (#135760) #135923

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release/20.x: [LoongArch] Don't crash on instruction prefetch intrinsics (#135760) #135923

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16 changes: 15 additions & 1 deletion llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);

setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
setOperationAction(ISD::PREFETCH, MVT::Other, Custom);

// Expand bitreverse.i16 with native-width bitrev and shift for now, before
// we get to know which of sll and revb.2h is faster.
Expand Down Expand Up @@ -459,10 +459,24 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
return lowerBITREVERSE(Op, DAG);
case ISD::SCALAR_TO_VECTOR:
return lowerSCALAR_TO_VECTOR(Op, DAG);
case ISD::PREFETCH:
return lowerPREFETCH(Op, DAG);
}
return SDValue();
}

SDValue LoongArchTargetLowering::lowerPREFETCH(SDValue Op,
SelectionDAG &DAG) const {
unsigned IsData = Op.getConstantOperandVal(4);

// We don't support non-data prefetch.
// Just preserve the chain.
if (!IsData)
return Op.getOperand(0);

return Op;
}

SDValue
LoongArchTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.h
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Expand Up @@ -337,6 +337,7 @@ class LoongArchTargetLowering : public TargetLowering {
SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerBITREVERSE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;

bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;
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33 changes: 33 additions & 0 deletions llvm/test/CodeGen/LoongArch/prefetchi.ll
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@@ -0,0 +1,33 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64

declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind

define dso_local void @prefetch_no_offset(ptr %ptr) nounwind {
; LA32-LABEL: prefetch_no_offset:
; LA32: # %bb.0: # %entry
; LA32-NEXT: ret
;
; LA64-LABEL: prefetch_no_offset:
; LA64: # %bb.0: # %entry
; LA64-NEXT: ret
entry:
tail call void @llvm.prefetch(ptr %ptr, i32 0, i32 3, i32 0)
ret void
}


define dso_local void @prefetch_with_offset(ptr %ptr) nounwind {
; LA32-LABEL: prefetch_with_offset:
; LA32: # %bb.0: # %entry
; LA32-NEXT: ret
;
; LA64-LABEL: prefetch_with_offset:
; LA64: # %bb.0: # %entry
; LA64-NEXT: ret
entry:
%addr = getelementptr i8, ptr %ptr, i64 200
tail call void @llvm.prefetch(ptr %addr, i32 0, i32 3, i32 0)
ret void
}
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