[AArch64] Use helper class for emitting CFI instructions into MIR (NFCI) #136004
+78
−178
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
s-barannikov
requested review from
ostannard,
dhoekwater,
MacDue and
davemgreen
|
@llvm/pr-subscribers-backend-aarch64 Author: Sergei Barannikov (s-barannikov) ChangesSimilar to #135994 and #135845. Patch is 24.68 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/136004.diff 4 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/CFIInstBuilder.h b/llvm/include/llvm/CodeGen/CFIInstBuilder.h
index e799b47a0c974..7bd513330dfe0 100644
--- a/llvm/include/llvm/CodeGen/CFIInstBuilder.h
+++ b/llvm/include/llvm/CodeGen/CFIInstBuilder.h
@@ -63,8 +63,8 @@ class CFIInstBuilder {
nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
}
- void buildDefCFAOffset(int64_t Offset) const {
- insertCFIInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset));
+ void buildDefCFAOffset(int64_t Offset, MCSymbol *Label = nullptr) const {
+ insertCFIInst(MCCFIInstruction::cfiDefCfaOffset(Label, Offset));
}
void buildOffset(MCRegister Reg, int64_t Offset) const {
@@ -72,11 +72,24 @@ class CFIInstBuilder {
nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset));
}
+ void buildNegateRAState() const {
+ insertCFIInst(MCCFIInstruction::createNegateRAState(nullptr));
+ }
+
+ void buildNegateRAStateWithPC() const {
+ insertCFIInst(MCCFIInstruction::createNegateRAStateWithPC(nullptr));
+ }
+
void buildRestore(MCRegister Reg) const {
insertCFIInst(MCCFIInstruction::createRestore(
nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
}
+ void buildSameValue(MCRegister Reg) const {
+ insertCFIInst(MCCFIInstruction::createSameValue(
+ nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
+ }
+
void buildEscape(StringRef Bytes, StringRef Comment = "") const {
insertCFIInst(
MCCFIInstruction::createEscape(nullptr, Bytes, SMLoc(), Comment));
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 68218e59961c2..78ac57e3e92a6 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -216,6 +216,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -602,33 +603,23 @@ void AArch64FrameLowering::emitCalleeSavedGPRLocations(
if (CSI.empty())
return;
- const TargetSubtargetInfo &STI = MF.getSubtarget();
- const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
- const TargetInstrInfo &TII = *STI.getInstrInfo();
- DebugLoc DL = MBB.findDebugLoc(MBBI);
-
+ CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
for (const auto &Info : CSI) {
unsigned FrameIdx = Info.getFrameIdx();
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
continue;
assert(!Info.isSpilledToReg() && "Spilling to registers not implemented");
- int64_t DwarfReg = TRI.getDwarfRegNum(Info.getReg(), true);
int64_t Offset = MFI.getObjectOffset(FrameIdx) - getOffsetOfLocalArea();
// The location of VG will be emitted before each streaming-mode change in
// the function. Only locally-streaming functions require emitting the
// non-streaming VG location here.
if ((LocallyStreaming && FrameIdx == AFI->getStreamingVGIdx()) ||
- (!LocallyStreaming &&
- DwarfReg == TRI.getDwarfRegNum(AArch64::VG, true)))
+ (!LocallyStreaming && Info.getReg() == AArch64::VG))
continue;
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIBuilder.buildOffset(Info.getReg(), Offset);
}
}
@@ -644,9 +635,8 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations(
const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
- const TargetInstrInfo &TII = *STI.getInstrInfo();
- DebugLoc DL = MBB.findDebugLoc(MBBI);
AArch64FunctionInfo &AFI = *MF.getInfo<AArch64FunctionInfo>();
+ CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
for (const auto &Info : CSI) {
if (!(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
@@ -663,54 +653,32 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations(
StackOffset::getScalable(MFI.getObjectOffset(Info.getFrameIdx())) -
StackOffset::getFixed(AFI.getCalleeSavedStackSize(MFI));
- unsigned CFIIndex = MF.addFrameInst(createCFAOffset(TRI, Reg, Offset));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIBuilder.insertCFIInst(createCFAOffset(TRI, Reg, Offset));
}
}
-static void insertCFISameValue(const MCInstrDesc &Desc, MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator InsertPt,
- unsigned DwarfReg) {
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createSameValue(nullptr, DwarfReg));
- BuildMI(MBB, InsertPt, DebugLoc(), Desc).addCFIIndex(CFIIndex);
-}
-
void AArch64FrameLowering::resetCFIToInitialState(
MachineBasicBlock &MBB) const {
MachineFunction &MF = *MBB.getParent();
const auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
- const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
const auto &TRI =
static_cast<const AArch64RegisterInfo &>(*Subtarget.getRegisterInfo());
const auto &MFI = *MF.getInfo<AArch64FunctionInfo>();
- const MCInstrDesc &CFIDesc = TII.get(TargetOpcode::CFI_INSTRUCTION);
- DebugLoc DL;
+ CFIInstBuilder CFIBuilder(MBB, MBB.begin(), MachineInstr::NoFlags);
// Reset the CFA to `SP + 0`.
- MachineBasicBlock::iterator InsertPt = MBB.begin();
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
- nullptr, TRI.getDwarfRegNum(AArch64::SP, true), 0));
- BuildMI(MBB, InsertPt, DL, CFIDesc).addCFIIndex(CFIIndex);
+ CFIBuilder.buildDefCFA(AArch64::SP, 0);
// Flip the RA sign state.
- if (MFI.shouldSignReturnAddress(MF)) {
- auto CFIInst = MFI.branchProtectionPAuthLR()
- ? MCCFIInstruction::createNegateRAStateWithPC(nullptr)
- : MCCFIInstruction::createNegateRAState(nullptr);
- CFIIndex = MF.addFrameInst(CFIInst);
- BuildMI(MBB, InsertPt, DL, CFIDesc).addCFIIndex(CFIIndex);
- }
+ if (MFI.shouldSignReturnAddress(MF))
+ MFI.branchProtectionPAuthLR() ? CFIBuilder.buildNegateRAStateWithPC()
+ : CFIBuilder.buildNegateRAState();
// Shadow call stack uses X18, reset it.
if (MFI.needsShadowCallStackPrologueEpilogue(MF))
- insertCFISameValue(CFIDesc, MF, MBB, InsertPt,
- TRI.getDwarfRegNum(AArch64::X18, true));
+ CFIBuilder.buildSameValue(AArch64::X18);
// Emit .cfi_same_value for callee-saved registers.
const std::vector<CalleeSavedInfo> &CSI =
@@ -719,8 +687,7 @@ void AArch64FrameLowering::resetCFIToInitialState(
MCRegister Reg = Info.getReg();
if (!TRI.regNeedsCFI(Reg, Reg))
continue;
- insertCFISameValue(CFIDesc, MF, MBB, InsertPt,
- TRI.getDwarfRegNum(Reg, true));
+ CFIBuilder.buildSameValue(Reg);
}
}
@@ -736,8 +703,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
- const TargetInstrInfo &TII = *STI.getInstrInfo();
- DebugLoc DL = MBB.findDebugLoc(MBBI);
+ CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameDestroy);
for (const auto &Info : CSI) {
if (SVE !=
@@ -752,11 +718,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
if (!Info.isRestored())
continue;
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
- nullptr, TRI.getDwarfRegNum(Info.getReg(), true)));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameDestroy);
+ CFIBuilder.buildRestore(Info.getReg());
}
}
@@ -905,13 +867,8 @@ void AArch64FrameLowering::allocateStackSpace(
.addReg(TargetReg);
if (EmitCFI) {
// Set the CFA register back to SP.
- unsigned Reg =
- Subtarget.getRegisterInfo()->getDwarfRegNum(AArch64::SP, true);
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup)
+ .buildDefCFARegister(AArch64::SP);
}
if (RealignmentPadding)
AFI.setStackRealigned(true);
@@ -1552,13 +1509,9 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
InsertSEH(*MIB, *TII, FrameFlag);
}
- if (EmitCFI) {
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset - CSStackSizeInc));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(FrameFlag);
- }
+ if (EmitCFI)
+ CFIInstBuilder(MBB, MBBI, FrameFlag)
+ .buildDefCFAOffset(CFAOffset - CSStackSizeInc);
return std::prev(MBB.erase(MBBI));
}
@@ -1673,11 +1626,8 @@ static void emitShadowCallStackPrologue(const TargetInstrInfo &TII,
static_cast<char>(unsigned(dwarf::DW_OP_breg18)),
static_cast<char>(-8) & 0x7f, // addend (sleb128)
};
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createEscape(
- nullptr, StringRef(CFIInst, sizeof(CFIInst))));
- BuildMI(MBB, MBBI, DL, TII.get(AArch64::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameSetup);
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup)
+ .buildEscape(StringRef(CFIInst, sizeof(CFIInst)));
}
}
@@ -1694,34 +1644,25 @@ static void emitShadowCallStackEpilogue(const TargetInstrInfo &TII,
.addImm(-8)
.setMIFlag(MachineInstr::FrameDestroy);
- if (MF.getInfo<AArch64FunctionInfo>()->needsAsyncDwarfUnwindInfo(MF)) {
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, 18));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameDestroy);
- }
+ if (MF.getInfo<AArch64FunctionInfo>()->needsAsyncDwarfUnwindInfo(MF))
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameDestroy)
+ .buildRestore(AArch64::X18);
}
// Define the current CFA rule to use the provided FP.
static void emitDefineCFAWithFP(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, unsigned FixedObject) {
+ unsigned FixedObject) {
const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
const AArch64RegisterInfo *TRI = STI.getRegisterInfo();
- const TargetInstrInfo *TII = STI.getInstrInfo();
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
const int OffsetToFirstCalleeSaveFromFP =
AFI->getCalleeSaveBaseToFrameRecordOffset() -
AFI->getCalleeSavedStackSize();
Register FramePtr = TRI->getFrameRegister(MF);
- unsigned Reg = TRI->getDwarfRegNum(FramePtr, true);
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
- nullptr, Reg, FixedObject - OffsetToFirstCalleeSaveFromFP));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup)
+ .buildDefCFA(FramePtr, FixedObject - OffsetToFirstCalleeSaveFromFP);
}
#ifndef NDEBUG
@@ -1916,11 +1857,8 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
// Label used to tie together the PROLOG_LABEL and the MachineMoves.
MCSymbol *FrameLabel = MF.getContext().createTempSymbol();
// Encode the stack size of the leaf function.
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::cfiDefCfaOffset(FrameLabel, NumBytes));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup)
+ .buildDefCFAOffset(NumBytes, FrameLabel);
}
}
@@ -2026,7 +1964,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
}
}
if (EmitAsyncCFI)
- emitDefineCFAWithFP(MF, MBB, MBBI, DL, FixedObject);
+ emitDefineCFAWithFP(MF, MBB, MBBI, FixedObject);
}
// Now emit the moves for whatever callee saved regs we have (including FP,
@@ -2253,16 +2191,14 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
if (EmitCFI && !EmitAsyncCFI) {
if (HasFP) {
- emitDefineCFAWithFP(MF, MBB, MBBI, DL, FixedObject);
+ emitDefineCFAWithFP(MF, MBB, MBBI, FixedObject);
} else {
StackOffset TotalSize =
SVEStackSize + StackOffset::getFixed((int64_t)MFI.getStackSize());
- unsigned CFIIndex = MF.addFrameInst(createDefCFA(
- *RegInfo, /*FrameReg=*/AArch64::SP, /*Reg=*/AArch64::SP, TotalSize,
- /*LastAdjustmentWasScalable=*/false));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
+ CFIBuilder.insertCFIInst(
+ createDefCFA(*RegInfo, /*FrameReg=*/AArch64::SP, /*Reg=*/AArch64::SP,
+ TotalSize, /*LastAdjustmentWasScalable=*/false));
}
emitCalleeSavedGPRLocations(MBB, MBBI);
emitCalleeSavedSVELocations(MBB, MBBI);
@@ -2460,15 +2396,9 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
assert(!SVEStackSize && "Cannot combine SP bump with SVE");
// When we are about to restore the CSRs, the CFA register is SP again.
- if (EmitCFI && hasFP(MF)) {
- const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();
- unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, Reg, NumBytes));
- BuildMI(MBB, LastPopI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameDestroy);
- }
+ if (EmitCFI && hasFP(MF))
+ CFIInstBuilder(MBB, LastPopI, MachineInstr::FrameDestroy)
+ .buildDefCFA(AArch64::SP, NumBytes);
emitFrameOffset(MBB, MBB.getFirstTerminator(), DL, AArch64::SP, AArch64::SP,
StackOffset::getFixed(NumBytes + (int64_t)AfterCSRPopSize),
@@ -2587,15 +2517,9 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
MachineInstr::FrameDestroy, false, NeedsWinCFI, &HasWinCFI);
// When we are about to restore the CSRs, the CFA register is SP again.
- if (EmitCFI && hasFP(MF)) {
- const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();
- unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::cfiDefCfa(nullptr, Reg, PrologueSaveSize));
- BuildMI(MBB, LastPopI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameDestroy);
- }
+ if (EmitCFI && hasFP(MF))
+ CFIInstBuilder(MBB, LastPopI, MachineInstr::FrameDestroy)
+ .buildDefCFA(AArch64::SP, PrologueSaveSize);
// This must be placed after the callee-save restore code because that code
// assumes the SP is at the same location as it was after the callee-save save
@@ -4966,46 +4890,37 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
}
} // namespace
-MachineBasicBlock::iterator emitVGSaveRestore(MachineBasicBlock::iterator II,
- const AArch64FrameLowering *TFI) {
+static void emitVGSaveRestore(MachineBasicBlock::iterator II,
+ const AArch64FrameLowering *TFI) {
MachineInstr &MI = *II;
MachineBasicBlock *MBB = MI.getParent();
MachineFunction *MF = MBB->getParent();
if (MI.getOpcode() != AArch64::VGSavePseudo &&
MI.getOpcode() != AArch64::VGRestorePseudo)
- return II;
+ return;
SMEAttrs FuncAttrs(MF->getFunction());
bool LocallyStreaming =
FuncAttrs.hasStreamingBody() && !FuncAttrs.hasStreamingInterface();
const AArch64FunctionInfo *AFI = MF->getInfo<AArch64FunctionInfo>();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
- const AArch64InstrInfo *TII =
- MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
int64_t VGFrameIdx =
LocallyStreaming ? AFI->getStreamingVGIdx() : AFI->getVGIdx();
assert(VGFrameIdx != std::numeric_limits<int>::max() &&
"Expected FrameIdx for VG");
- unsigned CFIIndex;
+ CFIInstBuilder CFIBuilder(*MBB, II, MachineInstr::NoFlags);
if (MI.getOpcode() == AArch64::VGSavePseudo) {
const MachineFrameInfo &MFI = MF->getFrameInfo();
int64_t Offset =
MFI.getObjectOffset(VGFrameIdx) - TFI->getOffsetOfLocalArea();
- CFIIndex = MF->addFrameInst(MCCFIInstruction::createOffset(
- nullptr, TRI->getDwarfRegNum(AArch64::VG, true), Offset));
- } else
- CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
- nullptr, TRI->getDwarfRegNum(AArch64::VG, true)));
-
- MachineInstr *UnwindInst = BuildMI(*MBB, II, II->getDebugLoc(),
- TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
+ CFIBuilder.buildOffset(AArch64::VG, Offset);
+ } else {
+ CFIBuilder.buildRestore(AArch64::VG);
+ }
MI.eraseFromParent();
- return UnwindInst->getIterator();
}
void AArch64FrameLowering::processFunctionBeforeFrameIndicesReplaced(
@@ -5013,8 +4928,8 @@ void AArch64FrameLowering::processFunctionBeforeFrameIndicesReplaced(
for (auto &BB : MF)
for (MachineBasicBlock::iterator II = BB.begin(); II != BB.end();) {
if (requiresSaveVG(MF))
- II = emitVGSaveRestore(II, this);
- if (StackTaggingMergeSetTag)
+ emitVGSaveRestore(II++, this);
+ else if (StackTaggingMergeSetTag)
II = tryMergeAdjacentSTG(II, this, RS);
}
}
@@ -5361,14 +5276,8 @@ void AArch64FrameLowering::inlineStackProbeFixed(
MBB = MBBI->getParent();
if (EmitAsyncCFI && !HasFP) {
// Set the CFA register back to SP.
- const AArch64RegisterInfo &RegInfo =
- *MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
- unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
- BuildMI(*MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder(*MBB, MBBI, MachineInstr::FrameSetup)
+ .buildDefCFARegister(AArch64::SP);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 74217fad82a7e..8e9ac82b5acd6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -21,6 +21,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
@@ -9879,24 +9880,14 @@ void AArch64InstrInfo::buildOutlinedFrame(
It = MBB.insert(It, STRXpre);
if (MF.getInfo<AArch64FunctionInfo>()->needsDwarfUnwindInfo(MF)) {
- const TargetSubtargetInfo &STI = MF.getSubtarget();
- const MCRegisterInfo *MRI = STI.getRegisterInfo();
- unsigned DwarfReg = MRI->getDwarfRegNum(AArch64::LR, true);
+ CFIInstBuilder CFIBuilder(MBB, It, MachineInstr::FrameSetup);
// Add a CFI saying the stack was moved 16 B down.
- int64_t StackPosE...
[truncated]
|
s-barannikov
changed the title
dhoekwater
approved these changes
Apr 17, 2025
| BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) | ||
| .addCFIIndex(CFIIndex) | ||
| .setMIFlags(MachineInstr::FrameSetup); | ||
| CFIBuilder.buildOffset(Info.getReg(), Offset); |
There was a problem hiding this comment.
(Here and elsewhere) if CFIInstBuilder isn't too expensive to construct, it may be more readable to declare CFIBuilder closer to its use so it's clear you're building a MachineInstr::FrameSetup instruction.
Alternatively, you could get rid of the local variable entirely and do CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup).buildOffset(Info.getReg(), Offset) instead.
There was a problem hiding this comment.
It is not exactly expensive, but it contains a couple of virtual calls, so we should probably avoid constructing it in loops like this. Most other places use temporaries as in your second suggestion.
I can assure you that it looks much more readable on a local machine than on github 🙂
dhoekwater
approved these changes
Apr 17, 2025
llvm-sync bot
pushed a commit
to arm/arm-toolchain
that referenced
this pull request
Apr 18, 2025
…nto MIR (NFCI) (#136004) Pull Request: llvm/llvm-project#136004
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/18/builds/14737 Here is the relevant piece of the build log for the reference |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Similar to #135994 and #135845.