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Merged
merged 3 commits into from
Apr 28, 2025
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[LoongArch] Try to widen shuffle mask #136081

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3d6badb
Try to widen shuffle mask
tangaac Apr 17, 2025
247d3a7
widen shuffle mask as late as possible
tangaac Apr 17, 2025
18c72db
update tests
tangaac Apr 23, 2025
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36 changes: 36 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include <llvm/Analysis/VectorUtils.h>

using namespace llvm;

Expand Down Expand Up @@ -543,6 +544,37 @@ SDValue LoongArchTargetLowering::lowerBITREVERSE(SDValue Op,
}
}

// Widen element type to get a new mask value (if possible).
// For example:
// shufflevector <4 x i32> %a, <4 x i32> %b,
// <4 x i32> <i32 6, i32 7, i32 2, i32 3>
// is equivalent to:
// shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 1>
// can be lowered to:
// VPACKOD_D vr0, vr0, vr1
static SDValue widenShuffleMask(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
SDValue V1, SDValue V2, SelectionDAG &DAG) {
unsigned EltBits = VT.getScalarSizeInBits();

if (EltBits > 32 || EltBits == 1)
return SDValue();

SmallVector<int, 8> NewMask;
if (widenShuffleMaskElts(Mask, NewMask)) {
MVT NewEltVT = VT.isFloatingPoint() ? MVT::getFloatingPointVT(EltBits * 2)
: MVT::getIntegerVT(EltBits * 2);
MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
SDValue NewV1 = DAG.getBitcast(NewVT, V1);
SDValue NewV2 = DAG.getBitcast(NewVT, V2);
return DAG.getBitcast(
VT, DAG.getVectorShuffle(NewVT, DL, NewV1, NewV2, NewMask));
}
}

return SDValue();
}

/// Attempts to match a shuffle mask against the VBSLL, VBSRL, VSLLI and VSRLI
/// instruction.
// The funciton matches elements from one of the input vector shuffled to the
Expand Down Expand Up @@ -1365,6 +1397,8 @@ static SDValue lower128BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
return Result;
if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, Mask, VT, V1, V2, DAG)))
return Result;
if (SDValue NewShuffle = widenShuffleMask(DL, Mask, VT, V1, V2, DAG))
return NewShuffle;
if ((Result = lowerVECTOR_SHUFFLE_VSHUF(DL, Mask, VT, V1, V2, DAG)))
return Result;
return SDValue();
Expand Down Expand Up @@ -1803,6 +1837,8 @@ static SDValue lower256BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
return Result;
if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, NewMask, VT, V1, V2, DAG)))
return Result;
if (SDValue NewShuffle = widenShuffleMask(DL, NewMask, VT, V1, V2, DAG))
return NewShuffle;
if ((Result = lowerVECTOR_SHUFFLE_XVSHUF(DL, NewMask, VT, V1, V2, DAG)))
return Result;

Expand Down
39 changes: 15 additions & 24 deletions llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
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Expand Up @@ -6,7 +6,8 @@ define <32 x i8> @widen_shuffle_mask_v32i8_to_v16i16(<32 x i8> %a, <32 x i8> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI0_0)
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0
; CHECK-NEXT: xvori.b $xr0, $xr2, 0
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Is the xvori.b instruction redundant in this context? Since it effectively acts as a no-op copy from $xr2 to $xr0, it might be possible to eliminate it entirely by adjusting the destination of the preceding xvshuf.h instruction. If that's safe to do here, consider folding this into the current patch.

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Is the xvori.b instruction redundant in this context? Since it effectively acts as a no-op copy from $xr2 to $xr0, it might be possible to eliminate it entirely by adjusting the destination of the preceding xvshuf.h instruction. If that's safe to do here, consider folding this into the current patch.

This test uses vector register to pass parameters, so xvori.b is necessary.
The loss of xvori.b is acceptable, we widen shuffle mask before lower it to vshuf, so it still has chance to be lowerd to other shuffle instructions.

v32i8 -> v16i16 ---- can't be widenen anymore ----> xvshuf.h 
                ---- can be widened to v8i32 ----> v8i32 -> xvpackev.w

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Thanks. Just to clarify - are you assuming $xr0 is used as a return value here? If so, would the following be equivalent?

; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI0_0)
; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI0_0)
; CHECK-NEXT:    xvshuf.h $xr0, $xr1, $xr0

Under the native ABI, the 256-bit vector return values typically go through the stack, not $xr registers. If we're confident xvori.b isn't needed, it might be worth double-checking how this behaves with native ABI return conventions.

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Thanks, xvori.b is indeed redundant.
May we should use pointer instead vector in these lasx ir tests.

define void @widen_shuffle_mask_v32i8_to_v16i16(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: widen_shuffle_mask_v32i8_to_v16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xvld	$xr1, $a0, 0
; CHECK-NEXT:    xvld	$xr2, $a1, 0
; CHECK-NEXT:    pcalau12i	$a0, %pc_hi20(.LCPI0_0)
; CHECK-NEXT:    xvld $xr0, $a0, %pc_lo12(.LCPI0_0)
; CHECK-NEXT:    xvshuf.h $xr0, $xr2, $xr1
; CHECK-NEXT:    ret
    %1 = load <32 x i8>, ptr %a
    %2 = load <32 x i8>, ptr %b
    %r = shufflevector <32 x i8> %1, <32 x i8> %2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 32, i32 33, i32 34, i32 35, i32 24, i32 25, i32 26, i32 27, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 30, i32 31>
    store <32 x i8> %r, ptr %c
    ret void
}

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@heiher heiher Apr 26, 2025 •
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Ah, I see -- since the xd operand in xvshuf.h serves as both input and output, the use of xvori.b is indeed necessary. Looks good to me.

; CHECK-NEXT: ret
%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 32, i32 33, i32 34, i32 35, i32 24, i32 25, i32 26, i32 27, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 30, i32 31>
ret <32 x i8> %r
Expand All @@ -17,7 +18,8 @@ define <32 x i8> @widen_shuffle_mask_v32i8_to_v8i32(<32 x i8> %a, <32 x i8> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI1_0)
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
; CHECK-NEXT: xvori.b $xr0, $xr2, 0
; CHECK-NEXT: ret
%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 32, i32 33, i32 34, i32 35, i32 24, i32 25, i32 26, i32 27, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 62, i32 63>
ret <32 x i8> %r
Expand All @@ -28,7 +30,8 @@ define <32 x i8> @widen_shuffle_mask_v32i8_to_v4i64(<32 x i8> %a, <32 x i8> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI2_0)
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
; CHECK-NEXT: xvori.b $xr0, $xr2, 0
; CHECK-NEXT: ret
%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
ret <32 x i8> %r
Expand All @@ -39,7 +42,7 @@ define <16 x i16> @widen_shuffle_mask_v16i16_to_v8i32(<16 x i16> %a, <16 x i16>
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI3_0)
; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
; CHECK-NEXT: xvori.b $xr0, $xr2, 0
; CHECK-NEXT: ret
%r = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 6, i32 7, i32 16, i32 17, i32 2, i32 3, i32 10, i32 11, i32 12, i32 13, i32 24, i32 25, i32 26, i32 27>
Expand All @@ -51,7 +54,7 @@ define <16 x i16> @widen_shuffle_mask_v16i16_to_v4i64(<16 x i16> %a, <16 x i16>
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI4_0)
; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0
; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
; CHECK-NEXT: xvori.b $xr0, $xr2, 0
; CHECK-NEXT: ret
%r = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
Expand All @@ -63,7 +66,7 @@ define <8 x i32> @widen_shuffle_mask_v8i32_to_v4i64(<8 x i32> %a, <8 x i32> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI5_0)
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
; CHECK-NEXT: xvori.b $xr0, $xr2, 0
; CHECK-NEXT: ret
%r = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 14, i32 15, i32 6, i32 7>
Expand All @@ -73,9 +76,7 @@ define <8 x i32> @widen_shuffle_mask_v8i32_to_v4i64(<8 x i32> %a, <8 x i32> %b)
define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpackev_h(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvpackev_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI6_0)
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvpackev.h $xr0, $xr1, $xr0
; CHECK-NEXT: ret
%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 32, i32 33, i32 4, i32 5, i32 36, i32 37, i32 8, i32 9, i32 40, i32 41, i32 12, i32 13, i32 44, i32 45, i32 16, i32 17, i32 48, i32 49, i32 20, i32 21, i32 52, i32 53, i32 24, i32 25, i32 56, i32 57, i32 28, i32 29, i32 60, i32 61>
ret <32 x i8> %r
Expand All @@ -84,9 +85,7 @@ define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpackev_h(<32 x i8> %a, <32 x i8>
define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpackod_h(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvpackod_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI7_0)
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvpackod.h $xr0, $xr1, $xr0
; CHECK-NEXT: ret
%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 2, i32 3, i32 34, i32 35, i32 6, i32 7, i32 38, i32 39, i32 10, i32 11, i32 42, i32 43, i32 14, i32 15, i32 46, i32 47, i32 18, i32 19, i32 50, i32 51, i32 22, i32 23, i32 54, i32 55, i32 26, i32 27, i32 58, i32 59, i32 30, i32 31, i32 62, i32 63>
ret <32 x i8> %r
Expand All @@ -95,9 +94,7 @@ define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpackod_h(<32 x i8> %a, <32 x i8>
define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpickev_h(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvpickev_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI8_0)
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvpickev.h $xr0, $xr1, $xr0
; CHECK-NEXT: ret
%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 32, i32 33, i32 36, i32 37, i32 40, i32 41, i32 44, i32 45, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29, i32 48, i32 49, i32 52, i32 53, i32 56, i32 57, i32 60, i32 61>
ret <32 x i8> %r
Expand All @@ -106,9 +103,7 @@ define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpickev_h(<32 x i8> %a, <32 x i8>
define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpickod_h(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvpickod_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI9_0)
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvpickod.h $xr0, $xr1, $xr0
; CHECK-NEXT: ret
%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 2, i32 3, i32 6, i32 7, i32 10, i32 11, i32 14, i32 15, i32 34, i32 35, i32 38, i32 39, i32 42, i32 43, i32 46, i32 47, i32 18, i32 19, i32 22, i32 23, i32 26, i32 27, i32 30, i32 31, i32 50, i32 51, i32 54, i32 55, i32 58, i32 59, i32 62, i32 63>
ret <32 x i8> %r
Expand All @@ -117,9 +112,7 @@ define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpickod_h(<32 x i8> %a, <32 x i8>
define <32 x i8> @widen_shuffle_mask_v32i8_to_xvilvl_h(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvilvl_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI10_0)
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvilvl.h $xr0, $xr1, $xr0
; CHECK-NEXT: ret
%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 32, i32 33, i32 2, i32 3, i32 34, i32 35, i32 4, i32 5, i32 36, i32 37, i32 6, i32 7, i32 38, i32 39, i32 16, i32 17, i32 48, i32 49, i32 18, i32 19, i32 50, i32 51, i32 20, i32 21, i32 52, i32 53, i32 22, i32 23, i32 54, i32 55>
ret <32 x i8> %r
Expand All @@ -128,9 +121,7 @@ define <32 x i8> @widen_shuffle_mask_v32i8_to_xvilvl_h(<32 x i8> %a, <32 x i8> %
define <32 x i8> @widen_shuffle_mask_v32i8_to_xvilvh_h(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvilvh_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI11_0)
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvilvh.h $xr0, $xr1, $xr0
; CHECK-NEXT: ret
%r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 8, i32 9, i32 40, i32 41, i32 10, i32 11, i32 42, i32 43, i32 12, i32 13, i32 44, i32 45, i32 14, i32 15, i32 46, i32 47, i32 24, i32 25, i32 56, i32 57, i32 26, i32 27, i32 58, i32 59, i32 28, i32 29, i32 60, i32 61, i32 30, i32 31, i32 62, i32 63>
ret <32 x i8> %r
Expand Down
39 changes: 15 additions & 24 deletions llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,8 @@ define <16 x i8> @widen_shuffle_mask_v16i8_to_v8i16(<16 x i8> %a, <16 x i8> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI0_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vshuf.h $vr2, $vr1, $vr0
; CHECK-NEXT: vori.b $vr0, $vr2, 0
; CHECK-NEXT: ret
%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 24, i32 25, i32 26, i32 27, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 2, i32 3>
ret <16 x i8> %r
Expand All @@ -17,7 +18,8 @@ define <16 x i8> @widen_shuffle_mask_v16i8_to_v4i32(<16 x i8> %a, <16 x i8> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI1_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
; CHECK-NEXT: vori.b $vr0, $vr2, 0
; CHECK-NEXT: ret
%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
ret <16 x i8> %r
Expand All @@ -28,7 +30,8 @@ define <16 x i8> @widen_shuffle_mask_v16i8_to_v2i64(<16 x i8> %a, <16 x i8> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI2_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
; CHECK-NEXT: vori.b $vr0, $vr2, 0
; CHECK-NEXT: ret
%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
ret <16 x i8> %r
Expand All @@ -39,7 +42,7 @@ define <8 x i16> @widen_shuffle_mask_v8i16_to_v4i32(<8 x i16> %a, <8 x i16> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI3_0)
; CHECK-NEXT: vshuf.h $vr2, $vr1, $vr0
; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
; CHECK-NEXT: vori.b $vr0, $vr2, 0
; CHECK-NEXT: ret
%r = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 12, i32 13, i32 14, i32 15, i32 2, i32 3>
Expand All @@ -51,7 +54,7 @@ define <8 x i16> @widen_shuffle_mask_v8i16_to_v2i64(<8 x i16> %a, <8 x i16> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI4_0)
; CHECK-NEXT: vshuf.h $vr2, $vr1, $vr0
; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
; CHECK-NEXT: vori.b $vr0, $vr2, 0
; CHECK-NEXT: ret
%r = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
Expand All @@ -63,7 +66,7 @@ define <4 x i32> @widen_shuffle_mask_v4i32_to_v2i64(<4 x i32> %a, <4 x i32> %b)
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI5_0)
; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
; CHECK-NEXT: vori.b $vr0, $vr2, 0
; CHECK-NEXT: ret
%r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
Expand All @@ -73,9 +76,7 @@ define <4 x i32> @widen_shuffle_mask_v4i32_to_v2i64(<4 x i32> %a, <4 x i32> %b)
define <16 x i8> @widen_shuffle_mask_v16i8_to_vpackev_h(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vpackev_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI6_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vpackev.h $vr0, $vr1, $vr0
; CHECK-NEXT: ret
%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 4, i32 5, i32 20, i32 21, i32 8, i32 9, i32 24, i32 25, i32 12, i32 13, i32 28, i32 29>
ret <16 x i8> %r
Expand All @@ -84,9 +85,7 @@ define <16 x i8> @widen_shuffle_mask_v16i8_to_vpackev_h(<16 x i8> %a, <16 x i8>
define <16 x i8> @widen_shuffle_mask_v16i8_to_vpackod_h(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vpackod_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI7_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vpackod.h $vr0, $vr1, $vr0
; CHECK-NEXT: ret
%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 18, i32 19, i32 6, i32 7, i32 22, i32 23, i32 10, i32 11, i32 26, i32 27, i32 14, i32 15, i32 30, i32 31>
ret <16 x i8> %r
Expand All @@ -95,9 +94,7 @@ define <16 x i8> @widen_shuffle_mask_v16i8_to_vpackod_h(<16 x i8> %a, <16 x i8>
define <16 x i8> @widen_shuffle_mask_v16i8_to_vpickev_h(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vpickev_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI8_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vpickev.h $vr0, $vr1, $vr0
; CHECK-NEXT: ret
%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
ret <16 x i8> %r
Expand All @@ -106,9 +103,7 @@ define <16 x i8> @widen_shuffle_mask_v16i8_to_vpickev_h(<16 x i8> %a, <16 x i8>
define <16 x i8> @widen_shuffle_mask_v16i8_to_vpickod_h(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vpickod_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI9_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vpickod.h $vr0, $vr1, $vr0
; CHECK-NEXT: ret
%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 6, i32 7, i32 10, i32 11, i32 14, i32 15, i32 18, i32 19, i32 22, i32 23, i32 26, i32 27, i32 30, i32 31>
ret <16 x i8> %r
Expand All @@ -117,9 +112,7 @@ define <16 x i8> @widen_shuffle_mask_v16i8_to_vpickod_h(<16 x i8> %a, <16 x i8>
define <16 x i8> @widen_shuffle_mask_v16i8_to_vilvl_h(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vilvl_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI10_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
; CHECK-NEXT: ret
%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
ret <16 x i8> %r
Expand All @@ -128,9 +121,7 @@ define <16 x i8> @widen_shuffle_mask_v16i8_to_vilvl_h(<16 x i8> %a, <16 x i8> %b
define <16 x i8> @widen_shuffle_mask_v16i8_to_vilvh_h(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vilvh_h:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI11_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vilvh.h $vr0, $vr1, $vr0
; CHECK-NEXT: ret
%r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
ret <16 x i8> %r
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