[clang][RISCV] support BITINT with mixed-type#156592
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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Pull Request Overview
This PR implements mixed-type support for BITINT in RISC-V by making type extension based on the variable type rather than using sign extension for all cases, aligning with the RISC-V ELF PSABI specification.
Key changes:
- Updates RISC-V ABI handling to use appropriate extension (zero/sign) based on BitInt signedness
- Adds comprehensive test coverage for signed, unsigned, and default BitInt types across different bit widths
- Modifies existing test expectations to reflect the new signext behavior for signed BitInt parameters
Reviewed Changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated 1 comment.
| File | Description |
|---|---|
| clang/test/CodeGen/ext-int-cc.c | Updates test expectations to include signext attribute for RISC-V BitInt parameters |
| clang/test/CodeGen/RISCV/bitint.c | Adds comprehensive test cases for BitInt operations with different signedness and bit widths |
| clang/lib/CodeGen/Targets/RISCV.cpp | Implements the core ABI changes to handle BitInt extension based on type signedness |
clang/lib/CodeGen/Targets/RISCV.cpp
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| // FIXME: Maybe we should treat 32 as a special case and wait for | ||
| // the SPEC to decide. |
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The FIXME comment indicates uncertainty about handling 32-bit BitInt types and references waiting for a specification decision. This suggests the implementation may be incomplete or temporary for this specific case.
Suggested change
| // FIXME: Maybe we should treat 32 as a special case and wait for | |
| // the SPEC to decide. | |
| // FIXME: The handling of 32-bit BitIntType is currently unspecified by the ABI. | |
| // As a conservative approach, pass 32-bit BitIntType as direct without extension. | |
| if (EIT->getNumBits() == 32) | |
| return ABIArgInfo::getDirect(); | |
| if (EIT->getNumBits() < 32) | |
| return extendType(Ty, CGT.ConvertType(Ty)); |
topperc
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Sep 3, 2025
clang/lib/CodeGen/Targets/RISCV.cpp
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| // the SPEC to decide. | ||
| if (EIT->getNumBits() <= 2 * XLen) | ||
| return ABIArgInfo::getExtend(Ty, CGT.ConvertType(Ty)); | ||
| if (EIT->getNumBits() > 128 || |
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Is the existing code with hasInt128Type, correct for the new ABI?
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I think it's fine. And after this patch, I only assume updating the signed/unsigned extension between 0 and 2×XLEN.
The other part match the following rule.
0~XLEN pass by value(reg)
XLEN~2xXLEN pass by value(reg pair)
> 2xXLEN pass be reference(mem)
cc @kito-cheng
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Isn't the EIT->getNumBits() > 64 check always true after your change?
And it looks like for RV32, any size between 65 bits and 128 bits will pass directly when -fforce-enable-int128 is passed. Why is _BitInt behavior affected by -fforce-enable-int128?
llvmbot
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@llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-clang Author: Piyou Chen (BeMg) ChangesImplement riscv-non-isa/riscv-elf-psabi-doc#419. This patch makes the type extension based on the variable type for BIGINT, rather than using sign extension for all cases. Full diff: https://github.com/llvm/llvm-project/pull/156592.diff 3 Files Affected:
diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp
index 0ef39b68eb6e3..be2f5d5355f24 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -680,14 +680,11 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
if (const auto *ED = Ty->getAsEnumDecl())
Ty = ED->getIntegerType();
- // All integral types are promoted to XLen width
- if (Size < XLen && Ty->isIntegralOrEnumerationType()) {
- return extendType(Ty, CGT.ConvertType(Ty));
- }
-
if (const auto *EIT = Ty->getAs<BitIntType>()) {
- if (EIT->getNumBits() < XLen)
- return extendType(Ty, CGT.ConvertType(Ty));
+ // FIXME: Maybe we should treat 32 as a special case and wait for
+ // the psABI to decide.
+ if (EIT->getNumBits() <= 2 * XLen)
+ return ABIArgInfo::getExtend(Ty, CGT.ConvertType(Ty));
if (EIT->getNumBits() > 128 ||
(!getContext().getTargetInfo().hasInt128Type() &&
EIT->getNumBits() > 64))
@@ -696,6 +693,10 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
/*ByVal=*/false);
}
+ // All integral types are promoted to XLen width
+ if (Size < XLen && Ty->isIntegralOrEnumerationType())
+ return extendType(Ty, CGT.ConvertType(Ty));
+
return ABIArgInfo::getDirect();
}
diff --git a/clang/test/CodeGen/RISCV/bitint.c b/clang/test/CodeGen/RISCV/bitint.c
new file mode 100644
index 0000000000000..2c28c536dc1bc
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/bitint.c
@@ -0,0 +1,233 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature
+// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=RISCV64
+// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=RISCV32
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_17_add_unsigned
+// RISCV64-SAME: (i17 noundef zeroext [[A:%.*]], i17 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add i17 [[B]], [[A]]
+// RISCV64-NEXT: ret i17 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_17_add_unsigned
+// RISCV32-SAME: (i17 noundef zeroext [[A:%.*]], i17 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[ADD:%.*]] = add i17 [[B]], [[A]]
+// RISCV32-NEXT: ret i17 [[ADD]]
+//
+unsigned _BitInt(17) test_bitint_17_add_unsigned(unsigned _BitInt(17) a, unsigned _BitInt(17) b) {
+ return a + b;
+}
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_17_add_signed
+// RISCV64-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]
+// RISCV64-NEXT: ret i17 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_17_add_signed
+// RISCV32-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]
+// RISCV32-NEXT: ret i17 [[ADD]]
+//
+signed _BitInt(17) test_bitint_17_add_signed(signed _BitInt(17) a, signed _BitInt(17) b) {
+ return a + b;
+}
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_17_add_default
+// RISCV64-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]
+// RISCV64-NEXT: ret i17 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_17_add_default
+// RISCV32-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]]
+// RISCV32-NEXT: ret i17 [[ADD]]
+//
+_BitInt(17) test_bitint_17_add_default(_BitInt(17) a, _BitInt(17) b) {
+ return a + b;
+}
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_32_add_unsigned
+// RISCV64-SAME: (i32 noundef zeroext [[A:%.*]], i32 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add i32 [[B]], [[A]]
+// RISCV64-NEXT: ret i32 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_32_add_unsigned
+// RISCV32-SAME: (i32 noundef zeroext [[A:%.*]], i32 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[ADD:%.*]] = add i32 [[B]], [[A]]
+// RISCV32-NEXT: ret i32 [[ADD]]
+//
+unsigned _BitInt(32) test_bitint_32_add_unsigned(unsigned _BitInt(32) a, unsigned _BitInt(32) b) {
+ return a + b;
+}
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_32_add_signed
+// RISCV64-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]
+// RISCV64-NEXT: ret i32 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_32_add_signed
+// RISCV32-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]
+// RISCV32-NEXT: ret i32 [[ADD]]
+//
+signed _BitInt(32) test_bitint_32_add_signed(signed _BitInt(32) a, signed _BitInt(32) b) {
+ return a + b;
+}
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_32_add_default
+// RISCV64-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]
+// RISCV64-NEXT: ret i32 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_32_add_default
+// RISCV32-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]]
+// RISCV32-NEXT: ret i32 [[ADD]]
+//
+_BitInt(32) test_bitint_32_add_default(_BitInt(32) a, _BitInt(32) b) {
+ return a + b;
+}
+
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned
+// RISCV64-SAME: (i65 noundef zeroext [[A:%.*]], i65 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]]
+// RISCV64-NEXT: ret i65 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned
+// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6:![0-9]+]]
+// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65
+// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]
+// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65
+// RISCV32-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]]
+// RISCV32-NEXT: [[STOREDV4:%.*]] = zext i65 [[ADD]] to i128
+// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]
+// RISCV32-NEXT: ret void
+//
+unsigned _BitInt(65) test_bitint_65_add_unsigned(unsigned _BitInt(65) a, unsigned _BitInt(65) b) {
+ return a + b;
+}
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_65_add_signed
+// RISCV64-SAME: (i65 noundef signext [[A:%.*]], i65 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]
+// RISCV64-NEXT: ret i65 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_signed
+// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]]
+// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65
+// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]
+// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65
+// RISCV32-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]
+// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128
+// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]
+// RISCV32-NEXT: ret void
+//
+signed _BitInt(65) test_bitint_65_add_signed(signed _BitInt(65) a, signed _BitInt(65) b) {
+ return a + b;
+}
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_65_add_default
+// RISCV64-SAME: (i65 noundef signext [[A:%.*]], i65 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]
+// RISCV64-NEXT: ret i65 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_default
+// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]]
+// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65
+// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]]
+// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65
+// RISCV32-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]]
+// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128
+// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]]
+// RISCV32-NEXT: ret void
+//
+_BitInt(65) test_bitint_65_add_default(_BitInt(65) a, _BitInt(65) b) {
+ return a + b;
+}
+
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned
+// RISCV64-SAME: (i77 noundef zeroext [[A:%.*]], i77 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]]
+// RISCV64-NEXT: ret i77 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned
+// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10:![0-9]+]]
+// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77
+// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]
+// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77
+// RISCV32-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]]
+// RISCV32-NEXT: [[STOREDV4:%.*]] = zext i77 [[ADD]] to i128
+// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]
+// RISCV32-NEXT: ret void
+//
+unsigned _BitInt(77) test_bitint_77_add_unsigned(unsigned _BitInt(77) a, unsigned _BitInt(77) b) {
+ return a + b;
+}
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_77_add_signed
+// RISCV64-SAME: (i77 noundef signext [[A:%.*]], i77 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]
+// RISCV64-NEXT: ret i77 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_signed
+// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]]
+// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77
+// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]
+// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77
+// RISCV32-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]
+// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128
+// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]
+// RISCV32-NEXT: ret void
+//
+signed _BitInt(77) test_bitint_77_add_signed(signed _BitInt(77) a, signed _BitInt(77) b) {
+ return a + b;
+}
+
+// RISCV64-LABEL: define {{[^@]+}}@test_bitint_77_add_default
+// RISCV64-SAME: (i77 noundef signext [[A:%.*]], i77 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// RISCV64-NEXT: entry:
+// RISCV64-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]
+// RISCV64-NEXT: ret i77 [[ADD]]
+//
+// RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_default
+// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] {
+// RISCV32-NEXT: entry:
+// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]]
+// RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77
+// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]]
+// RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77
+// RISCV32-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]]
+// RISCV32-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128
+// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]]
+// RISCV32-NEXT: ret void
+//
+_BitInt(77) test_bitint_77_add_default(_BitInt(77) a, _BitInt(77) b) {
+ return a + b;
+}
diff --git a/clang/test/CodeGen/ext-int-cc.c b/clang/test/CodeGen/ext-int-cc.c
index 7cfd992fd48b4..f845afcf1e087 100644
--- a/clang/test/CodeGen/ext-int-cc.c
+++ b/clang/test/CodeGen/ext-int-cc.c
@@ -49,8 +49,8 @@ void ParamPassing(_BitInt(128) b, _BitInt(64) c) {}
// R600: define{{.*}} void @ParamPassing(ptr addrspace(5) byval(i128) align 8 %{{.+}}, i64 %{{.+}})
// ARC: define{{.*}} void @ParamPassing(ptr byval(i128) align 4 %{{.+}}, i64 inreg %{{.+}})
// XCORE: define{{.*}} void @ParamPassing(ptr byval(i128) align 4 %{{.+}}, i64 %{{.+}})
-// RISCV64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
-// RISCV32: define{{.*}} void @ParamPassing(ptr dead_on_return %{{.+}}, i64 %{{.+}})
+// RISCV64: define{{.*}} void @ParamPassing(i128 signext %{{.+}}, i64 signext %{{.+}})
+// RISCV32: define{{.*}} void @ParamPassing(ptr dead_on_return %{{.+}}, i64 signext %{{.+}})
// WASM: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
// SYSTEMZ: define{{.*}} void @ParamPassing(ptr dead_on_return %{{.+}}, i64 %{{.+}})
// PPC64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
@@ -79,8 +79,8 @@ void ParamPassing2(_BitInt(127) b, _BitInt(63) c) {}
// R600: define{{.*}} void @ParamPassing2(ptr addrspace(5) byval(i128) align 8 %{{.+}}, i63 %{{.+}})
// ARC: define{{.*}} void @ParamPassing2(ptr byval(i128) align 4 %{{.+}}, i63 inreg %{{.+}})
// XCORE: define{{.*}} void @ParamPassing2(ptr byval(i128) align 4 %{{.+}}, i63 %{{.+}})
-// RISCV64: define{{.*}} void @ParamPassing2(i127 %{{.+}}, i63 signext %{{.+}})
-// RISCV32: define{{.*}} void @ParamPassing2(ptr dead_on_return %{{.+}}, i63 %{{.+}})
+// RISCV64: define{{.*}} void @ParamPassing2(i127 signext %{{.+}}, i63 signext %{{.+}})
+// RISCV32: define{{.*}} void @ParamPassing2(ptr dead_on_return %{{.+}}, i63 signext %{{.+}})
// WASM: define{{.*}} void @ParamPassing2(i127 %{{.+}}, i63 %{{.+}})
// SYSTEMZ: define{{.*}} void @ParamPassing2(ptr dead_on_return %{{.+}}, i63 signext %{{.+}})
// PPC64: define{{.*}} void @ParamPassing2(i127 %{{.+}}, i63 signext %{{.+}})
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Contributor
Author
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Update:
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Contributor
Author
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Update: make RV64 _BitInt(32) always signext |
topperc
reviewed
Sep 22, 2025
| /*ByVal=*/false); | ||
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| if (EIT->getNumBits() <= 2 * XLen) | ||
| return ABIArgInfo::getExtend(Ty, CGT.ConvertType(Ty)); |
Collaborator
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Can we call extendType here and remove the special case for 32 above? Looks like extendType will call ABIArgInfo::getExtend if its not the special case.
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There's something a bit strange happening here.
Ty: BitIntType 0xf7c7930 'unsigned _BitInt(17)
will be treated as 32 in
int TySize = getContext().getTypeSize(Ty);
If we use the extendType directly, unsigned _BitInt(17) will turn into a signed extension in this case.
Collaborator
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I'm guessing the call to getContext().getTypeSize(Ty) in that function returned the size rounded up to a byte.
I guess we can leave it how you have it then.
kito-cheng
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Oct 14, 2025
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LGTM, I believe the ABI side is stable enough and I gonna to implement same thing on GCC side :)
akadutta
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Oct 14, 2025
Implement riscv-non-isa/riscv-elf-psabi-doc#419. This patch makes the type extension based on the variable type for BIGINT, rather than using sign extension for all cases.
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Implement riscv-non-isa/riscv-elf-psabi-doc#419.
This patch makes the type extension based on the variable type for BIGINT, rather than using sign extension for all cases.