[libclc] Update default triple support for AMD and deprecate 32-bit PTX

[jhuber6]

Summary:
The standard nvptx target is not supported and has been completely
removed following the CUDA 12 release. It should be safe to drop support
for it in the default build. Additionally we add the amd vendor to the
amdgcn triple as this is the more canonical form and builds the same IR.

[jhuber6]

For the libclc developers, what's the expected way to get the spirv / clsprv targets to work? They always result in this failure for me.

cd /home/jhuber/Documents/llvm/llvm-project/build/runtimes/runtimes-x86_64-unknown-linux-gnu-bins/libclc && /usr/local/bin/llvm-spirv --spirv-max-version=1.1 -o /home/jhuber/Documents/llvm/llvm-project/build/./lib/clang/22/lib/libclc/spirv64-mesa3d-.spv /home/jhuber/Documents/llvm/llvm-project/build/runtimes/runtimes-x86_64-unknown-linux-gnu-bins/libclc/obj.libclc.dir/spirv64-mesa3d-/builtins.link.spirv64-mesa3d-.bc
Unknown attribute kind (105) (Producer: 'LLVM22.0.0git' Reader: 'LLVM 22.0.0git')

[arsenm]

You can't use tools build against old llvm for new bitcode

[wenju-he]

There are two ways to build libclc spirv targets:

• clone https://github.com/KhronosGroup/SPIRV-LLVM-Translator to llvm/projects/SPIRV-LLVM-Translator and add -DLLVM_EXTERNAL_PROJECTS="llvm-spirv" -DLIBCLC_TARGETS_TO_BUILD="all" to cmake command.
• add -DLIBCLC_USE_SPIRV_BACKEND=ON -DLIBCLC_TARGETS_TO_BUILD="all" to cmake command. This method should be preferrable but the build is very slow, which is tracked in Memory leak in SPIRV? #170339

[wenju-he]

update comment

llvm-project/libclc/cmake/modules/AddLibclc.cmake

Line 491 in 8516e7e

# * nvptx-- targets don't include workitem builtins

to nvptx64--?

[jhuber6]

update comment

llvm-project/libclc/cmake/modules/AddLibclc.cmake

Line 491 in 8516e7e

# * nvptx-- targets don't include workitem builtins

to nvptx64--?

Done, somewhat related, why is this a restriction on NVPTX? We should have access to the same block / thread indexing that AMDGCN has.

I need to figure out how to get SPIRV working with my gpuintrin.h interface so I can replace all of those functions with that header. Would you be opposed to that? if I recall the main blocker was the lack of a subgroup ballot intrinsic for SPIR-V.

[jhuber6]

For your downstream use, I already fixed the COV flag and #174454 should fix the wchar issue. I don't know why you need the last hack around the -mcpu options. Do you know how libclc handles ISA specific code? It seems to just do aliases.

[wenju-he]

Done, somewhat related, why is this a restriction on NVPTX? We should have access to the same block / thread indexing that AMDGCN has.

the comment might be outdated.

I need to figure out how to get SPIRV working with my gpuintrin.h interface so I can replace all of those functions with that header. Would you be opposed to that? if I recall the main blocker was the lack of a subgroup ballot intrinsic for SPIR-V.

no objection from me. Do you mean using gpuintrin.h in libclc implementation?

[wenju-he]

LGTM

[jhuber6]

no objection from me. Do you mean using gpuintrin.h in libclc implementation?

Yep, they're supposed to be generic wrappers around a lot of common GPU intrinsics, similar to what OpenCL would provide but done through a header. Like __gpu_thread_id(__GPU_DIM_X) which correctly dispatches to the intrinsic for AMDGCN / PTX. This is already used in the libc / openmp libraries.

[wenju-he]

Yep, they're supposed to be generic wrappers around a lot of common GPU intrinsics, similar to what OpenCL would provide but done through a header. Like __gpu_thread_id(__GPU_DIM_X) which correctly dispatches to the intrinsic for AMDGCN / PTX. This is already used in the libc / openmp libraries.

thanks, it LGTM that common code is unified at a place.

[wenju-he]

For your downstream use, I already fixed the COV flag and #174454 should fix the wchar issue. I don't know why you need the last hack around the -mcpu options.

thanks. target-cpu hack is not needed because -mlink-builtin-bitcode will ignore and replace it at

llvm-project/clang/lib/CodeGen/CodeGenAction.cpp

Line 207 in f54dd47

CodeGen::mergeDefaultFunctionDefinitionAttributes(

Incompatible target-features still have the issue as mentioned in the comment https://github.com/intel/llvm/blob/4decbf0da29f7daba8a87361456a264a331e2b5d/libclc/utils/prepare-builtins.cpp#L129-L146, but I think it is our downstream issue. We probably need to build multiple libspirv libraries and use compatible libspirv library for the target that user code is compiled for.

Do you know how libclc handles ISA specific code? It seems to just do aliases.

As I know, only amdgpu has ISA specific handling using different targets at

llvm-project/libclc/CMakeLists.txt

Lines 205 to 208 in f54dd47

	set( r600--_devices cedar cypress barts cayman )
	set( amdgcn--_devices tahiti )
	set( amdgcn-mesa-mesa3d_devices ${amdgcn--_devices} )
	set( amdgcn--amdhsa_devices none )

and aliases more ISAs to the appropriate target.