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release/22.x: Revert "[LoongArch] Lowering flog2 to flogb (#162978)" #176874

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c-rhodes merged 1 commit into from
Jan 20, 2026
Merged

release/22.x: Revert "[LoongArch] Lowering flog2 to flogb (#162978)" #176874

c-rhodes merged 1 commit into from
Jan 20, 2026

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@llvmbot llvmbot commented Jan 20, 2026

Backport 009e0cc

Requested by: @wangleiat

@llvmbot llvmbot added this to the LLVM 22.x Release milestone Jan 20, 2026
@github-project-automation github-project-automation bot moved this to Needs Triage in LLVM Release Status Jan 20, 2026
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llvmbot commented Jan 20, 2026

@ylzsx What do you think about merging this PR to the release branch?

@llvmbot llvmbot requested a review from ylzsx January 20, 2026 08:18
@llvmbot llvmbot mentioned this pull request Jan 20, 2026
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llvmbot commented Jan 20, 2026

@llvm/pr-subscribers-backend-loongarch

Author: None (llvmbot)

Changes

Backport 009e0cc

Requested by: @wangleiat

Patch is 25.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/176874.diff

8 Files Affected:

  • (modified) llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td (-1)
  • (modified) llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td (-1)
  • (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+2-8)
  • (modified) llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td (-3)
  • (modified) llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (-3)
  • (modified) llvm/test/CodeGen/LoongArch/ir-instruction/flog2.ll (+4-4)
  • (modified) llvm/test/CodeGen/LoongArch/lasx/ir-instruction/flog2.ll (+244-14)
  • (modified) llvm/test/CodeGen/LoongArch/lsx/ir-instruction/flog2.ll (+142-14)
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
index 32954b6c0d03f..17ca0b532842b 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
@@ -370,7 +370,6 @@ def : Pat<(f32 (uint_to_fp (i64 (sexti32 (i64 GPR:$src))))),
 // FP Rounding
 let Predicates = [HasBasicF, IsLA64] in {
 def : PatFpr<frint, FRINT_S, FPR32>;
-def : PatFpr<flog2, FLOGB_S, FPR32>;
 } // Predicates = [HasBasicF, IsLA64]
 
 let Predicates = [HasBasicF, IsLA32] in {
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
index e6cad1b33aa23..d365e315f00d5 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
@@ -349,7 +349,6 @@ def : Pat<(bitconvert FPR64:$src), (MOVFR2GR_D FPR64:$src)>;
 // FP Rounding
 let Predicates = [HasBasicD, IsLA64] in {
 def : PatFpr<frint, FRINT_D, FPR64>;
-def : PatFpr<flog2, FLOGB_D, FPR64>;
 } // Predicates = [HasBasicD, IsLA64]
 
 /// Pseudo-instructions needed for the soft-float ABI with LA32D
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index be9089208ebb5..bc9ae3eafb3b2 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -245,10 +245,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FP_TO_BF16, MVT::f32,
                        Subtarget.isSoftFPABI() ? LibCall : Custom);
 
-    if (Subtarget.is64Bit()) {
+    if (Subtarget.is64Bit())
       setOperationAction(ISD::FRINT, MVT::f32, Legal);
-      setOperationAction(ISD::FLOG2, MVT::f32, Legal);
-    }
 
     if (!Subtarget.hasBasicD()) {
       setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
@@ -294,10 +292,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FP_TO_BF16, MVT::f64,
                        Subtarget.isSoftFPABI() ? LibCall : Custom);
 
-    if (Subtarget.is64Bit()) {
+    if (Subtarget.is64Bit())
       setOperationAction(ISD::FRINT, MVT::f64, Legal);
-      setOperationAction(ISD::FLOG2, MVT::f64, Legal);
-    }
   }
 
   // Set operations for 'LSX' feature.
@@ -369,7 +365,6 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::FMA, VT, Legal);
       setOperationAction(ISD::FSQRT, VT, Legal);
       setOperationAction(ISD::FNEG, VT, Legal);
-      setOperationAction(ISD::FLOG2, VT, Legal);
       setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
                          ISD::SETUGE, ISD::SETUGT},
                         VT, Expand);
@@ -459,7 +454,6 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::FMA, VT, Legal);
       setOperationAction(ISD::FSQRT, VT, Legal);
       setOperationAction(ISD::FNEG, VT, Legal);
-      setOperationAction(ISD::FLOG2, VT, Legal);
       setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
                          ISD::SETUGE, ISD::SETUGT},
                         VT, Expand);
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index d6af093411c3a..fa4b720e7ba98 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -1606,9 +1606,6 @@ def : Pat<(fma_nsz (fneg v4f64:$xj), v4f64:$xk, v4f64:$xa),
 // XVFSQRT_{S/D}
 defm : PatXrF<fsqrt, "XVFSQRT">;
 
-// XVFLOGB_{S/D}
-defm : PatXrF<flog2, "XVFLOGB">;
-
 // XVRECIP_{S/D}
 def : Pat<(fdiv vsplatf32_fpimm_eq_1, v8f32:$xj),
           (XVFRECIP_S v8f32:$xj)>;
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index 43ad3819029cf..da7b6e833c996 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -1816,9 +1816,6 @@ def : Pat<(fma_nsz (fneg v2f64:$vj), v2f64:$vk, v2f64:$va),
 // VFSQRT_{S/D}
 defm : PatVrF<fsqrt, "VFSQRT">;
 
-// VFLOGB_{S/D}
-defm : PatVrF<flog2, "VFLOGB">;
-
 // VFRECIP_{S/D}
 def : Pat<(fdiv vsplatf32_fpimm_eq_1, v4f32:$vj),
           (VFRECIP_S v4f32:$vj)>;
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/flog2.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/flog2.ll
index e02a2e7cce9b2..93fcd421e4bd7 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/flog2.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/flog2.ll
@@ -12,8 +12,8 @@ define float @flog2_s(float %x) nounwind {
 ;
 ; LA64-LABEL: flog2_s:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    flogb.s $fa0, $fa0
-; LA64-NEXT:    ret
+; LA64-NEXT:    pcaddu18i $t8, %call36(log2f)
+; LA64-NEXT:    jr $t8
   %y = call float @llvm.log2.f32(float %x)
   ret float %y
 }
@@ -25,8 +25,8 @@ define double @flog2_d(double %x) nounwind {
 ;
 ; LA64-LABEL: flog2_d:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    flogb.d $fa0, $fa0
-; LA64-NEXT:    ret
+; LA64-NEXT:    pcaddu18i $t8, %call36(log2)
+; LA64-NEXT:    jr $t8
   %y = call double @llvm.log2.f64(double %x)
   ret double %y
 }
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/flog2.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/flog2.ll
index 6b5f5751e5706..68f2e3ab488e1 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/flog2.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/flog2.ll
@@ -1,17 +1,166 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefix=LA64
 
 declare <8 x float> @llvm.log2.v8f32(<8 x float>)
 declare <4 x double> @llvm.log2.v4f64(<4 x double>)
 
 define void @flog2_v8f32(ptr %res, ptr %a) nounwind {
-; CHECK-LABEL: flog2_v8f32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xvld $xr0, $a1, 0
-; CHECK-NEXT:    xvflogb.s $xr0, $xr0
-; CHECK-NEXT:    xvst $xr0, $a0, 0
-; CHECK-NEXT:    ret
+; LA32-LABEL: flog2_v8f32:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    addi.w $sp, $sp, -128
+; LA32-NEXT:    st.w $ra, $sp, 124 # 4-byte Folded Spill
+; LA32-NEXT:    st.w $fp, $sp, 120 # 4-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $a1, 0
+; LA32-NEXT:    xvst $xr0, $sp, 80 # 32-byte Folded Spill
+; LA32-NEXT:    move $fp, $a0
+; LA32-NEXT:    xvpickve.w $xr0, $xr0, 5
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT:    vst $vr0, $sp, 48 # 16-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.w $xr0, $xr0, 4
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $xr0
+; LA32-NEXT:    vld $vr1, $sp, 48 # 16-byte Folded Reload
+; LA32-NEXT:    vextrins.w $vr0, $vr1, 16
+; LA32-NEXT:    xvst $xr0, $sp, 48 # 32-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.w $xr0, $xr0, 6
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT:    xvld $xr1, $sp, 48 # 32-byte Folded Reload
+; LA32-NEXT:    vextrins.w $vr1, $vr0, 32
+; LA32-NEXT:    xvst $xr1, $sp, 48 # 32-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.w $xr0, $xr0, 7
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT:    xvld $xr1, $sp, 48 # 32-byte Folded Reload
+; LA32-NEXT:    vextrins.w $vr1, $vr0, 48
+; LA32-NEXT:    xvst $xr1, $sp, 48 # 32-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.w $xr0, $xr0, 1
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT:    vst $vr0, $sp, 16 # 16-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.w $xr0, $xr0, 0
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $xr0
+; LA32-NEXT:    vld $vr1, $sp, 16 # 16-byte Folded Reload
+; LA32-NEXT:    vextrins.w $vr0, $vr1, 16
+; LA32-NEXT:    xvst $xr0, $sp, 16 # 32-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.w $xr0, $xr0, 2
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT:    xvld $xr1, $sp, 16 # 32-byte Folded Reload
+; LA32-NEXT:    vextrins.w $vr1, $vr0, 32
+; LA32-NEXT:    xvst $xr1, $sp, 16 # 32-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.w $xr0, $xr0, 3
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT:    xvld $xr1, $sp, 16 # 32-byte Folded Reload
+; LA32-NEXT:    vextrins.w $vr1, $vr0, 48
+; LA32-NEXT:    xvld $xr0, $sp, 48 # 32-byte Folded Reload
+; LA32-NEXT:    xvpermi.q $xr1, $xr0, 2
+; LA32-NEXT:    xvst $xr1, $fp, 0
+; LA32-NEXT:    ld.w $fp, $sp, 120 # 4-byte Folded Reload
+; LA32-NEXT:    ld.w $ra, $sp, 124 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 128
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: flog2_v8f32:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    addi.d $sp, $sp, -128
+; LA64-NEXT:    st.d $ra, $sp, 120 # 8-byte Folded Spill
+; LA64-NEXT:    st.d $fp, $sp, 112 # 8-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $a1, 0
+; LA64-NEXT:    xvst $xr0, $sp, 80 # 32-byte Folded Spill
+; LA64-NEXT:    move $fp, $a0
+; LA64-NEXT:    xvpickve.w $xr0, $xr0, 5
+; LA64-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2f)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT:    vst $vr0, $sp, 48 # 16-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.w $xr0, $xr0, 4
+; LA64-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2f)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0 killed $f0 def $xr0
+; LA64-NEXT:    vld $vr1, $sp, 48 # 16-byte Folded Reload
+; LA64-NEXT:    vextrins.w $vr0, $vr1, 16
+; LA64-NEXT:    xvst $xr0, $sp, 48 # 32-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.w $xr0, $xr0, 6
+; LA64-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2f)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT:    xvld $xr1, $sp, 48 # 32-byte Folded Reload
+; LA64-NEXT:    vextrins.w $vr1, $vr0, 32
+; LA64-NEXT:    xvst $xr1, $sp, 48 # 32-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.w $xr0, $xr0, 7
+; LA64-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2f)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT:    xvld $xr1, $sp, 48 # 32-byte Folded Reload
+; LA64-NEXT:    vextrins.w $vr1, $vr0, 48
+; LA64-NEXT:    xvst $xr1, $sp, 48 # 32-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.w $xr0, $xr0, 1
+; LA64-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2f)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT:    vst $vr0, $sp, 16 # 16-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.w $xr0, $xr0, 0
+; LA64-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2f)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0 killed $f0 def $xr0
+; LA64-NEXT:    vld $vr1, $sp, 16 # 16-byte Folded Reload
+; LA64-NEXT:    vextrins.w $vr0, $vr1, 16
+; LA64-NEXT:    xvst $xr0, $sp, 16 # 32-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.w $xr0, $xr0, 2
+; LA64-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2f)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT:    xvld $xr1, $sp, 16 # 32-byte Folded Reload
+; LA64-NEXT:    vextrins.w $vr1, $vr0, 32
+; LA64-NEXT:    xvst $xr1, $sp, 16 # 32-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 80 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.w $xr0, $xr0, 3
+; LA64-NEXT:    # kill: def $f0 killed $f0 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2f)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT:    xvld $xr1, $sp, 16 # 32-byte Folded Reload
+; LA64-NEXT:    vextrins.w $vr1, $vr0, 48
+; LA64-NEXT:    xvld $xr0, $sp, 48 # 32-byte Folded Reload
+; LA64-NEXT:    xvpermi.q $xr1, $xr0, 2
+; LA64-NEXT:    xvst $xr1, $fp, 0
+; LA64-NEXT:    ld.d $fp, $sp, 112 # 8-byte Folded Reload
+; LA64-NEXT:    ld.d $ra, $sp, 120 # 8-byte Folded Reload
+; LA64-NEXT:    addi.d $sp, $sp, 128
+; LA64-NEXT:    ret
 entry:
   %v = load <8 x float>, ptr %a
   %r = call <8 x float> @llvm.log2.v8f32(<8 x float> %v)
@@ -20,12 +169,93 @@ entry:
 }
 
 define void @flog2_v4f64(ptr %res, ptr %a) nounwind {
-; CHECK-LABEL: flog2_v4f64:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xvld $xr0, $a1, 0
-; CHECK-NEXT:    xvflogb.d $xr0, $xr0
-; CHECK-NEXT:    xvst $xr0, $a0, 0
-; CHECK-NEXT:    ret
+; LA32-LABEL: flog2_v4f64:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    addi.w $sp, $sp, -112
+; LA32-NEXT:    st.w $ra, $sp, 108 # 4-byte Folded Spill
+; LA32-NEXT:    st.w $fp, $sp, 104 # 4-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $a1, 0
+; LA32-NEXT:    xvst $xr0, $sp, 64 # 32-byte Folded Spill
+; LA32-NEXT:    move $fp, $a0
+; LA32-NEXT:    xvpickve.d $xr0, $xr0, 3
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 killed $xr0
+; LA32-NEXT:    bl log2
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
+; LA32-NEXT:    vst $vr0, $sp, 32 # 16-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 64 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.d $xr0, $xr0, 2
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 killed $xr0
+; LA32-NEXT:    bl log2
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 def $xr0
+; LA32-NEXT:    vld $vr1, $sp, 32 # 16-byte Folded Reload
+; LA32-NEXT:    vextrins.d $vr0, $vr1, 16
+; LA32-NEXT:    xvst $xr0, $sp, 32 # 32-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 64 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.d $xr0, $xr0, 1
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 killed $xr0
+; LA32-NEXT:    bl log2
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
+; LA32-NEXT:    vst $vr0, $sp, 16 # 16-byte Folded Spill
+; LA32-NEXT:    xvld $xr0, $sp, 64 # 32-byte Folded Reload
+; LA32-NEXT:    xvpickve.d $xr0, $xr0, 0
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 killed $xr0
+; LA32-NEXT:    bl log2
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 def $xr0
+; LA32-NEXT:    vld $vr1, $sp, 16 # 16-byte Folded Reload
+; LA32-NEXT:    vextrins.d $vr0, $vr1, 16
+; LA32-NEXT:    xvld $xr1, $sp, 32 # 32-byte Folded Reload
+; LA32-NEXT:    xvpermi.q $xr0, $xr1, 2
+; LA32-NEXT:    xvst $xr0, $fp, 0
+; LA32-NEXT:    ld.w $fp, $sp, 104 # 4-byte Folded Reload
+; LA32-NEXT:    ld.w $ra, $sp, 108 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 112
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: flog2_v4f64:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    addi.d $sp, $sp, -112
+; LA64-NEXT:    st.d $ra, $sp, 104 # 8-byte Folded Spill
+; LA64-NEXT:    st.d $fp, $sp, 96 # 8-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $a1, 0
+; LA64-NEXT:    xvst $xr0, $sp, 64 # 32-byte Folded Spill
+; LA64-NEXT:    move $fp, $a0
+; LA64-NEXT:    xvpickve.d $xr0, $xr0, 3
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
+; LA64-NEXT:    vst $vr0, $sp, 32 # 16-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 64 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.d $xr0, $xr0, 2
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 def $xr0
+; LA64-NEXT:    vld $vr1, $sp, 32 # 16-byte Folded Reload
+; LA64-NEXT:    vextrins.d $vr0, $vr1, 16
+; LA64-NEXT:    xvst $xr0, $sp, 32 # 32-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 64 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.d $xr0, $xr0, 1
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
+; LA64-NEXT:    vst $vr0, $sp, 16 # 16-byte Folded Spill
+; LA64-NEXT:    xvld $xr0, $sp, 64 # 32-byte Folded Reload
+; LA64-NEXT:    xvpickve.d $xr0, $xr0, 0
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 killed $xr0
+; LA64-NEXT:    pcaddu18i $ra, %call36(log2)
+; LA64-NEXT:    jirl $ra, $ra, 0
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 def $xr0
+; LA64-NEXT:    vld $vr1, $sp, 16 # 16-byte Folded Reload
+; LA64-NEXT:    vextrins.d $vr0, $vr1, 16
+; LA64-NEXT:    xvld $xr1, $sp, 32 # 32-byte Folded Reload
+; LA64-NEXT:    xvpermi.q $xr0, $xr1, 2
+; LA64-NEXT:    xvst $xr0, $fp, 0
+; LA64-NEXT:    ld.d $fp, $sp, 96 # 8-byte Folded Reload
+; LA64-NEXT:    ld.d $ra, $sp, 104 # 8-byte Folded Reload
+; LA64-NEXT:    addi.d $sp, $sp, 112
+; LA64-NEXT:    ret
 entry:
   %v = load <4 x double>, ptr %a
   %r = call <4 x double> @llvm.log2.v4f64(<4 x double> %v)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/flog2.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/flog2.ll
index 87cc7c6dbc708..e5e75ec617b51 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/flog2.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/flog2.ll
@@ -1,17 +1,98 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefix=LA64
 
 declare <4 x float> @llvm.log2.v4f32(<4 x float>)
 declare <2 x double> @llvm.log2.v2f64(<2 x double>)
 
 define void @flog2_v4f32(ptr %res, ptr %a) nounwind {
-; CHECK-LABEL: flog2_v4f32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vld $vr0, $a1, 0
-; CHECK-NEXT:    vflogb.s $vr0, $vr0
-; CHECK-NEXT:    vst $vr0, $a0, 0
-; CHECK-NEXT:    ret
+; LA32-LABEL: flog2_v4f32:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    addi.w $sp, $sp, -48
+; LA32-NEXT:    st.w $ra, $sp, 44 # 4-byte Folded Spill
+; LA32-NEXT:    st.w $fp, $sp, 40 # 4-byte Folded Spill
+; LA32-NEXT:    vld $vr0, $a1, 0
+; LA32-NEXT:    vst $vr0, $sp, 16 # 16-byte Folded Spill
+; LA32-NEXT:    move $fp, $a0
+; LA32-NEXT:    vreplvei.w $vr0, $vr0, 1
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $vr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT:    vst $vr0, $sp, 0 # 16-byte Folded Spill
+; LA32-NEXT:    vld $vr0, $sp, 16 # 16-byte Folded Reload
+; LA32-NEXT:    vreplvei.w $vr0, $vr0, 0
+; LA32-NEXT:    # kill: def $f0 killed $f0 killed $vr0
+; LA32-NEXT:    bl log2f
+; LA32-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT:    vl...
[truncated]

ylzsx
ylzsx approved these changes Jan 20, 2026
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LGTM

@github-project-automation github-project-automation bot moved this from Needs Triage to Needs Merge in LLVM Release Status Jan 20, 2026
@wangleiat @c-rhodes
Revert "[LoongArch] Lowering flog2 to flogb (llvm#162978)"
20a9be3 
This reverts commit d9e5e72.

The semantics of `flog2(x)` and `logb(x)` are different.

Fixes: llvm#176818

Reviewers: zhaoqi5, SixWeining, ylzsx

Pull Request: llvm#176850

(cherry picked from commit 009e0cc)
@c-rhodes c-rhodes merged commit 20a9be3 into llvm:release/22.x Jan 20, 2026
@github-project-automation github-project-automation bot moved this from Needs Merge to Done in LLVM Release Status Jan 20, 2026
@wangleiat wangleiat mentioned this pull request Jan 21, 2026
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