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[RISC-V][MC] Support RVY AUIPC instruction - #177074
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@llvm/pr-subscribers-backend-risc-v Author: Alexander Richardson (arichardson) ChangesFor RVY, the AUIPC instruction is mode-dependent, writing back a full This was made possible by the previous commits that introduced Patch is 21.19 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/177074.diff 4 Files Affected:
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 556c78dcc5617..8c87587220b2c 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -84,6 +84,17 @@ class RISCVAsmParser : public MCTargetAsmParser {
SMLoc getLoc() const { return getParser().getTok().getLoc(); }
bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureStdExtE); }
+ /// \return When true, pointers should use YGPR instead of GPR
+ bool isCapMode() const { return getSTI().hasFeature(RISCV::FeatureCapMode); }
+ unsigned getPtrAddiOpcode() const {
+ return isCapMode() ? RISCV::ADDIY : RISCV::ADDI;
+ }
+ unsigned getPtrLoadOpcode() const {
+ if (isCapMode())
+ return RISCV::LY;
+ return isRV64() ? RISCV::LD : RISCV::LW;
+ }
+
bool enableExperimentalExtension() const {
return getSTI().hasFeature(RISCV::Experimental);
}
@@ -1372,11 +1383,13 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);
- // In RVY mode, the BasePtrRC register class should select capability
+ // In RVY mode, the various Ptr register class should select capability
// registers for the base pointer operands, otherwise we use GPRs.
// TODO: Is there any way we could do this in tablegen automatically?
- if (Kind == MCK_RegByHwMode_BasePtrRC)
- Kind = STI->hasFeature(RISCV::FeatureCapMode) ? MCK_YGPRNoX0 : MCK_GPR;
+ if (Kind == MCK_RegByHwMode_PtrReg)
+ Kind = isCapMode() ? MCK_YGPR : MCK_GPR;
+ else if (Kind == MCK_RegByHwMode_BasePtrRC)
+ Kind = isCapMode() ? MCK_YGPRNoX0 : MCK_GPR;
if (Op.isGPR() && (Kind == MCK_YGPR || Kind == MCK_YGPRNoX0)) {
// GPR and capability GPR use the same register names, convert if required.
@@ -3601,7 +3614,7 @@ void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
MCRegister DestReg = Inst.getOperand(0).getReg();
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_PCREL_HI20,
- RISCV::ADDI, IDLoc, Out);
+ getPtrAddiOpcode(), IDLoc, Out);
}
void RISCVAsmParser::emitLoadGlobalAddress(MCInst &Inst, SMLoc IDLoc,
@@ -3614,7 +3627,7 @@ void RISCVAsmParser::emitLoadGlobalAddress(MCInst &Inst, SMLoc IDLoc,
// Lx rdest, %pcrel_lo(TmpLabel)(rdest)
MCRegister DestReg = Inst.getOperand(0).getReg();
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
- unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
+ unsigned SecondOpcode = getPtrLoadOpcode();
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_GOT_HI20,
SecondOpcode, IDLoc, Out);
}
@@ -3644,9 +3657,8 @@ void RISCVAsmParser::emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
// Lx rdest, %pcrel_lo(TmpLabel)(rdest)
MCRegister DestReg = Inst.getOperand(0).getReg();
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
- unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_TLS_GOT_HI20,
- SecondOpcode, IDLoc, Out);
+ getPtrLoadOpcode(), IDLoc, Out);
}
void RISCVAsmParser::emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc,
@@ -3660,7 +3672,7 @@ void RISCVAsmParser::emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc,
MCRegister DestReg = Inst.getOperand(0).getReg();
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_TLS_GD_HI20,
- RISCV::ADDI, IDLoc, Out);
+ getPtrAddiOpcode(), IDLoc, Out);
}
void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 36fe4dfa66610..bd534401318cf 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -227,13 +227,6 @@ def GPRMemZeroOffset : MemOperand<GPR> {
}
def GPRMem : MemOperand<GPR>;
-// Note: For RVY, the encodings using x0/zero (a null capability) as the base
-// are reserved. Therefore, we use YGPRNoX0 to reject them in the assembler
-// while allowing the encodings for RVI mode.
-def BasePtrRC : RegClassByHwMode<
- [RV32I, RV64I, RV32Y, RV64Y],
- [GPR, GPR, YGPRNoX0, YGPRNoX0]>;
-
def BasePtr : MemOperand<BasePtrRC>;
@@ -760,7 +753,7 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1,
def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
"lui", "$rd, $imm20">, Sched<[WriteIALU]>;
-def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
+def AUIPC : RVInstU<OPC_AUIPC, (outs PtrReg:$rd), (ins uimm20_auipc:$imm20),
"auipc", "$rd, $imm20">, Sched<[WriteIALU]>;
def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),
@@ -1240,7 +1233,7 @@ def : MnemonicAlias<"sbreak", "ebreak">;
def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
let Predicates = [HasStdExtZicfilp] in {
-def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>;
+def : InstAlias<"lpad $imm20", (AUIPC NullReg, uimm20:$imm20)>;
}
//===----------------------------------------------------------------------===//
@@ -1897,7 +1890,7 @@ def PseudoMovImm : Pseudo<(outs GPR:$dst), (ins i32imm:$imm), []>,
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, isCodeGenOnly = 0,
isAsmParserOnly = 1 in
-def PseudoLLA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+def PseudoLLA : Pseudo<(outs PtrReg:$dst), (ins bare_symbol:$src), [],
"lla", "$dst, $src">;
// Refer to comment on PseudoLI for explanation of Size=32
@@ -1912,12 +1905,12 @@ def : Pat<(riscv_lla tconstpool:$in), (PseudoLLA tconstpool:$in)>;
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 0,
isAsmParserOnly = 1 in
-def PseudoLGA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+def PseudoLGA : Pseudo<(outs PtrReg:$dst), (ins bare_symbol:$src), [],
"lga", "$dst, $src">;
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 0,
isAsmParserOnly = 1 in
-def PseudoLA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+def PseudoLA : Pseudo<(outs PtrReg:$dst), (ins bare_symbol:$src), [],
"la", "$dst, $src">;
// Refer to comment on PseudoLI for explanation of Size=32
@@ -1928,16 +1921,16 @@ def PseudoLAImm : Pseudo<(outs GPR:$rd), (ins ixlenimm_li_restricted:$imm), [],
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 0,
isAsmParserOnly = 1 in
-def PseudoLA_TLS_IE : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+def PseudoLA_TLS_IE : Pseudo<(outs PtrReg:$dst), (ins bare_symbol:$src), [],
"la.tls.ie", "$dst, $src">;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, isCodeGenOnly = 0,
isAsmParserOnly = 1 in
-def PseudoLA_TLS_GD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+def PseudoLA_TLS_GD : Pseudo<(outs PtrReg:$dst), (ins bare_symbol:$src), [],
"la.tls.gd", "$dst, $src">;
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 32, isCodeGenOnly = 0 in
-def PseudoLA_TLSDESC : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
+def PseudoLA_TLSDESC : Pseudo<(outs PtrReg:$dst), (ins bare_symbol:$src), [],
"la.tlsdesc", "$dst, $src">;
def TLSDESCCallSymbol : AsmOperandClass {
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 5fb69d7bcf80d..642a55f2c32c6 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -272,8 +272,8 @@ def XLenVT : ValueTypeByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
defvar XLenPairVT = untyped;
// Allow f64 in GPR for ZDINX on RV64.
-def XLenFVT : ValueTypeByHwMode<[RV64I, RV64Y],
- [f64, f64]>;
+def XLenFVT : ValueTypeByHwMode<[DefaultMode, RV64I, RV64Y],
+ [/*XLen*/i32, f64, f64]>;
def XLenPairFVT : ValueTypeByHwMode<[RV32I, RV32Y],
[f64, f64]>;
@@ -282,8 +282,8 @@ def XLenVecI8VT : ValueTypeByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
[v4i8, v8i8, v4i8, v8i8]>;
def XLenVecI16VT : ValueTypeByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
[v2i16, v4i16, v2i16, v4i16]>;
-def XLenVecI32VT : ValueTypeByHwMode<[RV64I, RV64Y],
- [v2i32, v2i32]>;
+def XLenVecI32VT : ValueTypeByHwMode<[DefaultMode, RV64I, RV64Y],
+ [/*XLen*/i32, v2i32, v2i32]>;
def XLenRI : RegInfoByHwMode<
[RV32I, RV64I, RV32Y, RV64Y],
[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>, RegInfo<64,64,64>]>;
@@ -333,6 +333,18 @@ def YGPR : RegisterClass<"RISCV", [YLenVT], 64,
let RegInfos = YLenRI;
}
+// Note: We have to use a multiclass here instead of inheriting from
+// RegClassByHwMode since tablegen does not allow subclasses.
+// TODO: could add a usage assert here that AddrRC is XLenVT and CapRC YLenVT?
+multiclass PtrRegClassByHwMode<RegisterClass AddrRC, RegisterClass CapRC> {
+ def "" : RegClassByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
+ [AddrRC, AddrRC, CapRC, CapRC]>;
+}
+
+// This register class represents a pointer: YLen in capability mode, XLen
+// otherwise. Used for mode-dependent instructions such as AUIPC/JALR.
+defm PtrReg : PtrRegClassByHwMode<GPR, YGPR>;
+
def GPRX0 : GPRRegisterClass<(add X0)>;
def GPRX1 : GPRRegisterClass<(add X1)> {
@@ -353,6 +365,10 @@ def YGPRNoX0 : GPRRegisterClass<(sub YGPR, X0_Y)> {
let DiagnosticType = "InvalidRegClassYGPRNoNull";
let DiagnosticString = GPRNoX0.DiagnosticString;
}
+// Note: For RVY, the encodings using x0/zero (a null capability) as the base
+// are reserved. Therefore, we use YGPRNoX0 to reject them in the assembler
+// while allowing the encodings for RVI mode.
+defm BasePtrRC : PtrRegClassByHwMode<GPR, YGPRNoX0>;
def GPRNoX2 : GPRRegisterClass<(sub GPR, X2)> {
let DiagnosticType = "InvalidRegClassGPRNoX2";
@@ -405,6 +421,8 @@ def GPRNoX31 : GPRRegisterClass<(sub GPR, X31)> {
let DiagnosticString = "register must be a GPR excluding t6 (x31)";
}
+def NullReg : RegisterByHwMode<PtrReg, [RV32I, RV64I, RV32Y, RV64Y],
+ [X0, X0, X0_Y, X0_Y]>;
//===----------------------------------------------------------------------===//
// Even-Odd GPR Pairs
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/RISCV/rvy/rvy-auipc.s b/llvm/test/MC/RISCV/rvy/rvy-auipc.s
new file mode 100644
index 0000000000000..187b54ab70470
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvy/rvy-auipc.s
@@ -0,0 +1,194 @@
+# RUN: llvm-mc --triple=riscv32 --mattr=+experimental-y,+cap-mode --riscv-no-aliases --show-encoding --show-inst < %s \
+# RUN: | FileCheck --check-prefixes=CHECK,CHECK-ASM,CHECK-CAP %s
+# RUN: llvm-mc --triple=riscv32 --mattr=+experimental-y,-cap-mode --riscv-no-aliases --show-encoding --show-inst < %s \
+# RUN: | FileCheck --check-prefixes=CHECK,CHECK-ASM,CHECK-INT,CHECK-INT-32 %s
+# RUN: llvm-mc --triple=riscv64 --mattr=+experimental-y,+cap-mode --riscv-no-aliases --show-encoding --show-inst < %s \
+# RUN: | FileCheck --check-prefixes=CHECK,CHECK-ASM,CHECK-CAP %s
+# RUN: llvm-mc --triple=riscv64 --mattr=+experimental-y,-cap-mode --riscv-no-aliases --show-encoding --show-inst < %s \
+# RUN: | FileCheck --check-prefixes=CHECK,CHECK-ASM,CHECK-INT,CHECK-INT-64 %s
+## Check that the capmode output can be dissassembled correctly (this previous triggered an assertion in RISCVMCInstrAnalysis)
+# RUN: llvm-mc --filetype=obj --triple=riscv32 --mattr=+experimental-y,+cap-mode < %s -o - \
+# RUN: | llvm-objdump --mattr=+experimental-y,-cap-mode -M no-aliases -d -r --no-print-imm-hex - \
+# RUN: | FileCheck --check-prefixes=CHECK,CHECK-OBJ %s
+
+# RUN: llvm-mc --triple=riscv64 --mattr=+experimental-y,+cap-mode --riscv-no-aliases --show-encoding --show-inst --defsym=RV64=1 < %s \
+# RUN: | FileCheck --check-prefixes=CHECK,CHECK-ASM,CHECK-CAP %s
+# RUN: llvm-mc --triple=riscv64 --mattr=+experimental-y,-cap-mode --riscv-no-aliases --show-encoding --show-inst --defsym=RV64=1 < %s \
+# RUN: | FileCheck --check-prefixes=CHECK,CHECK-ASM,CHECK-INT,CHECK-INT-64 %s
+# DISABLED: llvm-mc --filetype=obj --triple=riscv64 --mattr=+experimental-y,+cap-mode --defsym=RV64=1 < %s -o %t64.o
+# DISABLED: llvm-objdump --mattr=+experimental-y,-cap-mode -M no-aliases -d -r --no-print-imm-hex %t64.o \
+# DISABLED: | FileCheck --check-prefixes=CHECK,CHECK-OBJ %s
+# CHECK: auipc a0, 0
+# CHECK-ASM-SAME: # encoding: [0x17,0x05,0x00,0x00]
+# CHECK-ASM-NEXT: # <MCInst #[[#]] AUIPC{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Imm:0>>
+auipc a0, 0
+# CHECK-NEXT: auipc a0, 1
+# CHECK-ASM-SAME: # encoding: [0x17,0x15,0x00,0x00]
+# CHECK-ASM-NEXT: # <MCInst #[[#]] AUIPC{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Imm:1>>
+auipc a0, 1
+# CHECK-ASM-NEXT: auipc a0, %pcrel_hi(sym)
+# CHECK-ASM-SAME: # encoding: [0x17,0bAAAA0101,A,A]
+# CHECK-ASM-NEXT: # fixup A - offset: 0, value: %pcrel_hi(sym), kind: fixup_riscv_pcrel_hi20
+# CHECK-ASM-NEXT: # <MCInst #[[#]] AUIPC{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Expr:%pcrel_hi(sym)>>
+# CHECK-OBJ-NEXT: auipc a0, 0
+# CHECK-OBJ-NEXT: R_RISCV_PCREL_HI20 sym
+auipc a0, %pcrel_hi(sym)
+#
+## Test the pseudo expansions using AUIPC:
+#
+# CHECK-OBJ-EMPTY:
+# CHECK-NEXT: .Lpcrel_hi0
+# CHECK-ASM-NEXT: auipc a0, %pcrel_hi(sym)
+# CHECK-ASM-SAME: # encoding: [0x17,0bAAAA0101,A,A]
+# CHECK-ASM-NEXT: # fixup A - offset: 0, value: %pcrel_hi(sym), kind: fixup_riscv_pcrel_hi20
+# CHECK-ASM-NEXT: # <MCInst #[[#]] AUIPC{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Expr:%pcrel_hi(sym)>>
+# CHECK-INT-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
+# CHECK-INT-SAME: # encoding: [0x13,0x05,0bAAAA0101,A]
+# CHECK-INT-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi0), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-INT-NEXT: # <MCInst #[[#]] ADDI{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: addiy a0, a0, %pcrel_lo(.Lpcrel_hi0)
+# CHECK-CAP-SAME: # encoding: [0x1b,0x25,0bAAAA0101,A]
+# CHECK-CAP-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi0), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-CAP-NEXT: # <MCInst #[[#]] ADDIY{{$}}
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Expr:%pcrel_lo(.Lpcrel_hi0)>>
+# CHECK-OBJ-NEXT: auipc a0, 0
+# CHECK-OBJ-NEXT: R_RISCV_PCREL_HI20 sym
+# CHECK-OBJ-NEXT: addiy a0, a0, 0
+# CHECK-OBJ-NEXT: R_RISCV_PCREL_LO12_I .Lpcrel_hi0
+la a0, sym
+# CHECK-OBJ-EMPTY:
+# CHECK-NEXT: .Lpcrel_hi1
+# CHECK-ASM-NEXT: auipc a0, %pcrel_hi(sym)
+# CHECK-ASM-SAME: # encoding: [0x17,0bAAAA0101,A,A]
+# CHECK-ASM-NEXT: # fixup A - offset: 0, value: %pcrel_hi(sym), kind: fixup_riscv_pcrel_hi20
+# CHECK-ASM-NEXT: # <MCInst #[[#]] AUIPC{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Expr:%pcrel_hi(sym)>>
+# CHECK-INT-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
+# CHECK-INT-SAME: # encoding: [0x13,0x05,0bAAAA0101,A]
+# CHECK-INT-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi1), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-INT-NEXT: # <MCInst #[[#]] ADDI{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: addiy a0, a0, %pcrel_lo(.Lpcrel_hi1)
+# CHECK-CAP-SAME: # encoding: [0x1b,0x25,0bAAAA0101,A]
+# CHECK-CAP-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi1), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-CAP-NEXT: # <MCInst #[[#]] ADDIY{{$}}
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Expr:%pcrel_lo(.Lpcrel_hi1)>>
+# CHECK-OBJ-NEXT: auipc a0, 0
+# CHECK-OBJ-NEXT: R_RISCV_PCREL_HI20 sym
+# CHECK-OBJ-NEXT: addiy a0, a0, 0
+# CHECK-OBJ-NEXT: R_RISCV_PCREL_LO12_I .Lpcrel_hi1
+lla a0, sym
+# CHECK-OBJ-EMPTY:
+# CHECK-NEXT: .Lpcrel_hi2
+# CHECK-ASM-NEXT: auipc a0, %got_pcrel_hi(sym)
+# CHECK-ASM-SAME: # encoding: [0x17,0x05,0x00,0x00]
+# CHECK-ASM-NEXT: # fixup A - offset: 0, value: %got_pcrel_hi(sym), relocation type: 20
+# CHECK-ASM-NEXT: # <MCInst #[[#]] AUIPC{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Expr:%got_pcrel_hi(sym)>>
+# CHECK-INT-32-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi2)(a0)
+# CHECK-INT-32-SAME: # encoding: [0x03,0x25,0bAAAA0101,A]
+# CHECK-INT-32-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi2), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-INT-32-NEXT: # <MCInst #[[#]] LW{{$}}
+# CHECK-INT-64-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0)
+# CHECK-INT-64-SAME: # encoding: [0x03,0x35,0bAAAA0101,A]
+# CHECK-INT-64-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi2), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-INT-64-NEXT: # <MCInst #[[#]] LD{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: ly a0, %pcrel_lo(.Lpcrel_hi2)(a0)
+# CHECK-CAP-SAME: # encoding: [0x0f,0x45,0bAAAA0101,A]
+# CHECK-CAP-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi2), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-CAP-NEXT: # <MCInst #[[#]] LY{{$}}
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Expr:%pcrel_lo(.Lpcrel_hi2)>>
+# CHECK-OBJ-NEXT: auipc a0, 0
+# CHECK-OBJ-NEXT: R_RISCV_GOT_HI20 sym
+# CHECK-OBJ-NEXT: ly a0, 0(a0)
+# CHECK-OBJ-NEXT: R_RISCV_PCREL_LO12_I .Lpcrel_hi2
+lga a0, sym
+# CHECK-OBJ-EMPTY:
+# CHECK-NEXT: .Lpcrel_hi3
+# CHECK-ASM-NEXT: auipc a0, %tls_ie_pcrel_hi(sym)
+# CHECK-ASM-SAME: # encoding: [0x17,0x05,0x00,0x00]
+# CHECK-ASM-NEXT: # fixup A - offset: 0, value: %tls_ie_pcrel_hi(sym), relocation type: 21
+# CHECK-ASM-NEXT: # <MCInst #[[#]] AUIPC{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Expr:%tls_ie_pcrel_hi(sym)>>
+# CHECK-INT-32-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi3)(a0)
+# CHECK-INT-32-SAME: # encoding: [0x03,0x25,0bAAAA0101,A]
+# CHECK-INT-32-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi3), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-INT-32-NEXT: # <MCInst #[[#]] LW{{$}}
+# CHECK-INT-64-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi3)(a0)
+# CHECK-INT-64-SAME: # encoding: [0x03,0x35,0bAAAA0101,A]
+# CHECK-INT-64-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi3), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-INT-64-NEXT: # <MCInst #[[#]] LD{{$}}
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-INT-NEXT: # <MCOperand Reg:X10>
+# CHECK-CAP-NEXT: ly a0, %pcrel_lo(.Lpcrel_hi3)(a0)
+# CHECK-CAP-SAME: # encoding: [0x0f,0x45,0bAAAA0101,A]
+# CHECK-CAP-NEXT: # fixup A - offset: 0, value: %pcrel_lo(.Lpcrel_hi3), kind: fixup_riscv_pcrel_lo12_i
+# CHECK-CAP-NEXT: # <MCInst #[[#]] LY{{$}}
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-CAP-NEXT: # <MCOperand Reg:X10_Y>
+# CHECK-ASM-NEXT: # <MCOperand Expr:%pcrel_lo(.Lpcrel_hi3)>>
+# CHECK-OBJ-NEXT: auipc a0, 0
+# CHECK-OBJ-NEXT: R_RISCV_TLS_GOT_HI20 sym
+# CHECK-OBJ-NEXT: ly a0, 0(a0)
+# CHECK-OBJ-NEXT: R_RISCV_PCREL_LO12_I .Lpcrel_hi3
+la.tls.ie a0, sym
+# CHECK-OBJ-EMPTY:
+# CHECK-NEXT: .Lpcrel_hi4
+# CHECK-ASM-NEXT: auipc a0, %tls_gd_pcrel_hi(sym)
+# CHECK-ASM-SAME: # encoding: [0x17,0x05,0x00,0x00]
+# CHECK-ASM-NEXT: # fixup A - offse...
[truncated]
|
jrtc27
requested changes
Jan 21, 2026
Contributor
There was a problem hiding this comment.
The address (really pointer) generating pseudos need more changes due to the semantic differences (provenance) from CHERI, as done downstream. Also the TLS ones are ABI-dependent and we're in the process of changing them so I think it's premature to allow them for CHERI upstream.
🐧 Linux x64 Test ResultsThe build failed before running any tests. Click on a failure below to see the details. include/llvm/TargetParser/RISCVTargetParserDef.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/include/llvm/TargetParser/RISCVTargetParserDef.inclib/Target/RISCV/RISCVGenAsmMatcher.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenAsmMatcher.inclib/Target/RISCV/RISCVGenCompressInstEmitter.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenCompressInstEmitter.inclib/Target/RISCV/RISCVGenDAGISel.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenDAGISel.inclib/Target/RISCV/RISCVGenGlobalISel.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenGlobalISel.inclib/Target/RISCV/RISCVGenDisassemblerTables.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenDisassemblerTables.inclib/Target/RISCV/RISCVGenExegesis.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenExegesis.inclib/Target/RISCV/RISCVGenMCCodeEmitter.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenMCCodeEmitter.inclib/Target/RISCV/RISCVGenMCPseudoLowering.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenMCPseudoLowering.inclib/Target/RISCV/RISCVGenInstrInfo.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenInstrInfo.inclib/Target/RISCV/RISCVGenAsmWriter.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenAsmWriter.inclib/Target/RISCV/RISCVGenO0PreLegalizeGICombiner.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenO0PreLegalizeGICombiner.inclib/Target/RISCV/RISCVGenRegisterBank.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenRegisterBank.inclib/Target/RISCV/RISCVGenMacroFusion.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenMacroFusion.inclib/Target/RISCV/RISCVGenPreLegalizeGICombiner.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenPreLegalizeGICombiner.inclib/Target/RISCV/RISCVGenRegisterInfo.inc lib/Target/RISCV/RISCVGenRegisterInfoEnums.inc lib/Target/RISCV/RISCVGenRegisterInfoHeader.inc lib/Target/RISCV/RISCVGenRegisterInfoMCDesc.inc lib/Target/RISCV/RISCVGenRegisterInfoTargetDesc.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenRegisterInfo.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenRegisterInfoEnums.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenRegisterInfoHeader.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenRegisterInfoMCDesc.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenRegisterInfoTargetDesc.inclib/Target/RISCV/RISCVGenPostLegalizeGICombiner.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenPostLegalizeGICombiner.inclib/Target/RISCV/RISCVGenSearchableTables.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenSearchableTables.inclib/Target/RISCV/RISCVGenSDNodeInfo.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenSDNodeInfo.inclib/Target/RISCV/RISCVGenSubtargetInfo.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/RISCV/RISCVGenSubtargetInfo.incIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
🪟 Windows x64 Test ResultsThe build failed before running any tests. Click on a failure below to see the details. [code=1] include/llvm/TargetParser/RISCVTargetParserDef.inc[code=1] lib/Target/RISCV/RISCVGenAsmMatcher.inc[code=1] lib/Target/RISCV/RISCVGenAsmWriter.inc[code=1] lib/Target/RISCV/RISCVGenDAGISel.inc[code=1] lib/Target/RISCV/RISCVGenCompressInstEmitter.inc[code=1] lib/Target/RISCV/RISCVGenDisassemblerTables.inc[code=1] lib/Target/RISCV/RISCVGenGlobalISel.inc[code=1] lib/Target/RISCV/RISCVGenInstrInfo.inc[code=1] lib/Target/RISCV/RISCVGenExegesis.inc[code=1] lib/Target/RISCV/RISCVGenMCCodeEmitter.inc[code=1] lib/Target/RISCV/RISCVGenMCPseudoLowering.inc[code=1] lib/Target/RISCV/RISCVGenMacroFusion.inc[code=1] lib/Target/RISCV/RISCVGenPreLegalizeGICombiner.inc[code=1] lib/Target/RISCV/RISCVGenO0PreLegalizeGICombiner.inc[code=1] lib/Target/RISCV/RISCVGenPostLegalizeGICombiner.inc[code=1] lib/Target/RISCV/RISCVGenSDNodeInfo.inc[code=1] lib/Target/RISCV/RISCVGenSearchableTables.inc[code=1] lib/Target/RISCV/RISCVGenSubtargetInfo.inc[code=1] lib/Target/RISCV/RISCVGenRegisterBank.inc[code=1] lib/Target/RISCV/RISCVGenRegisterInfo.inc lib/Target/RISCV/RISCVGenRegisterInfoEnums.inc lib/Target/RISCV/RISCVGenRegisterInfoHeader.inc lib/Target/RISCV/RISCVGenRegisterInfoMCDesc.inc lib/Target/RISCV/RISCVGenRegisterInfoTargetDesc.incIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
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Should I just drop the pseudos for now? |
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This previously triggered an assertion in a test for RVY's AUIPC instruction that will be submitted as a follow up (llvm/llvm-project#177074). Pull Request: llvm/llvm-project#177071
arichardson
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January 21, 2026 08:11
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Jan 27, 2026
This previously triggered an assertion in a test for RVY's AUIPC instruction that will be submitted as a follow up (llvm/llvm-project#177074). Pull Request: llvm/llvm-project#177071
arichardson
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May 26, 2026
For RVY, the AUIPC instruction is mode-dependent, writing back a full capability (X*_Y) register in capability mode and a plain X register otherwise. This introduces the NullReg RegisterByHwMode to support the lpad InstAlias that uses a fixed register and therefore we have to use a register that varies by HwMode in the pattern. This was made possible by the previous commits that introduced `RegisterByHwMode`. An alternative would have been to try to support static resolution of the `RegClassByHwMode` based on the predicates, but that requires duplicating all `InstAlias`es, which would be fine in the single case here, but we also need this for JALR with lots of `InstAlias`es. Pull Request: llvm#177074
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This previously triggered an assertion in a test for RVY's AUIPC instruction that will be submitted as a follow up (llvm/llvm-project#177074). Pull Request: llvm/llvm-project#177071
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Jun 16, 2026
For RVY, the AUIPC instruction is mode-dependent, writing back a full capability (X*_Y) register in capability mode and a plain X register otherwise. This introduces the NullReg RegisterByHwMode to support the lpad InstAlias that uses a fixed register and therefore we have to use a register that varies by HwMode in the pattern. This was made possible by the previous commits that introduced `RegisterByHwMode`. An alternative would have been to try to support static resolution of the `RegClassByHwMode` based on the predicates, but that requires duplicating all `InstAlias`es, which would be fine in the single case here, but we also need this for JALR with lots of `InstAlias`es. Pull Request: llvm#177074
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Aug 31, 2026
This previously triggered an assertion in a test for RVY's AUIPC instruction that will be submitted as a follow up (llvm/llvm-project#177074). Pull Request: llvm/llvm-project#177071 (cherry picked from commit 4b0640a855d79945bb4018e4eb529d2877115a94)
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This previously triggered an assertion in a test for RVY's AUIPC instruction that will be submitted as a follow up (llvm/llvm-project#177074). Pull Request: llvm/llvm-project#177071 (cherry picked from commit 4b0640a855d79945bb4018e4eb529d2877115a94)
arichardson
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Sep 4, 2026
This previously triggered an assertion in a test for RVY's AUIPC instruction that will be submitted as a follow up (llvm/llvm-project#177074). Pull Request: llvm/llvm-project#177071 (cherry picked from commit 4b0640a855d79945bb4018e4eb529d2877115a94)
This was referenced Oct 9, 2026
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For RVY, the AUIPC instruction is mode-dependent, writing back a full capability (X*_Y) register in capability mode and a plain X register otherwise. This introduces the NullReg RegisterByHwMode to support the lpad InstAlias that uses a fixed register and therefore we have to use a register that varies by HwMode in the pattern. This was made possible by the previous commits that introduced `RegisterByHwMode`. An alternative would have been to try to support static resolution of the `RegClassByHwMode` based on the predicates, but that requires duplicating all `InstAlias`es, which would be fine in the single case here, but we also need this for JALR with lots of `InstAlias`es. The la.tls.ie/la.tls.gd pseudos are rejected in capability mode for now since their expansion depends on the pure-capability TLS ABI. Also make RISCVMCInstrAnalysis invalidate the tracked AUIPC value when an instruction writes the X*_Y register. Pull Request: llvm#177074
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For RVY, the AUIPC instruction is mode-dependent, writing back a full
capability (X*_Y) register in capability mode and a plain X register
otherwise. This introduces the NullReg RegisterByHwMode to support the
lpad InstAlias that uses a fixed register and therefore we have to use a
register that varies by HwMode in the pattern.
This was made possible by the previous commits that introduced
RegisterByHwMode. An alternative would have been to try to support staticresolution of the
RegClassByHwModebased on the predicates, but thatrequires duplicating all
InstAliases, which would be fine in the singlecase here, but we also need this for JALR with lots of
InstAliases.