[VPlan] Don't widen extractvalue with single scalar operand - #221146
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[VPlan] Don't widen extractvalue with single scalar operand#221146lukel97 wants to merge 1 commit into
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If the struct to extract isn't widened, e.g. because it's fed into an address computation for an interleave, don't widen the extractvalue. A single scalar extractvalue can still be executed ok. Fixes a crash reported in #219941 (comment)
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@llvm/pr-subscribers-vectorizers @llvm/pr-subscribers-llvm-transforms Author: Luke Lau (lukel97) ChangesIf the struct to extract isn't widened, e.g. because it's fed into an Fixes a crash reported in Full diff: https://github.com/llvm/llvm-project/pull/221146.diff 2 Files Affected:
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index d71369e73b002..c6cf142cb0fc3 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -6445,7 +6445,8 @@ VPRecipeBuilder::tryToCreateWidenNonPhiRecipe(VPSingleDefRecipe *R,
// We can only replicate an extractvalue if its operand generates per lane in
// the same block, otherwise we would need to extract a lane from its struct
// operand which is invalid.
- if (VPI->getOpcode() == Instruction::ExtractValue)
+ if (VPI->getOpcode() == Instruction::ExtractValue &&
+ !vputils::isSingleScalar(VPI->getOperand(0)))
if (VPRecipeBase *OpR = VPI->getOperand(0)->getDefiningRecipe())
if (!vputils::doesGeneratePerAllLanes(OpR) ||
OpR->getParent() != VPI->getParent())
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/extractvalue-single-scalar.ll b/llvm/test/Transforms/LoopVectorize/AArch64/extractvalue-single-scalar.ll
new file mode 100644
index 0000000000000..d6b25cbcb1baf
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/extractvalue-single-scalar.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt < %s -p loop-vectorize -mtriple aarch64 -S | FileCheck %s
+
+; The sadd.with.overflow is kept as a single scalar. Make sure we
+; don't widen the extractvalue.
+define void @f(ptr noalias %src, ptr noalias %dst, i32 %n) {
+; CHECK-LABEL: define void @f(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[N:%.*]]) {
+; CHECK-NEXT: [[ITER_CHECK:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -2
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = add nuw i32 [[TMP1]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP2]], 8
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
+; CHECK: [[VECTOR_SCEVCHECK]]:
+; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[N]], -2
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
+; CHECK-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP4]])
+; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
+; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
+; CHECK-NEXT: [[TMP5:%.*]] = icmp slt i32 [[MUL_RESULT]], 0
+; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP5]], [[MUL_OVERFLOW]]
+; CHECK-NEXT: br i1 [[TMP6]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
+; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ule i32 [[TMP2]], 32
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP2]], 31
+; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 32, i32 [[TMP7]]
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP2]], [[TMP9]]
+; CHECK-NEXT: [[TMP10:%.*]] = shl i32 [[N_VEC]], 1
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP11:%.*]] = shl nuw i32 [[INDEX]], 1
+; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 32
+; CHECK-NEXT: [[TMP13:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP12]], i32 0)
+; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP13]], 0
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[SRC]], i32 [[TMP14]]
+; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <32 x i8>, ptr [[TMP15]], align 1
+; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <32 x i8> [[WIDE_VEC]], <32 x i8> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i8> [[STRIDED_VEC]], i64 15
+; CHECK-NEXT: store i8 [[TMP16]], ptr [[DST]], align 1
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 32
+; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[VEC_EPILOG_ITER_CHECK:.*]]
+; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
+; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP9]], 8
+; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
+; CHECK: [[VEC_EPILOG_PH]]:
+; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP2]], 7
+; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[TMP18]], 0
+; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i32 8, i32 [[TMP18]]
+; CHECK-NEXT: [[N_VEC2:%.*]] = sub i32 [[TMP2]], [[TMP20]]
+; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[N_VEC2]], 1
+; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]
+; CHECK: [[VEC_EPILOG_VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX3:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT6:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP22:%.*]] = shl nuw i32 [[INDEX3]], 1
+; CHECK-NEXT: [[TMP23:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP22]], i32 0)
+; CHECK-NEXT: [[TMP24:%.*]] = extractvalue { i32, i1 } [[TMP23]], 0
+; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[SRC]], i32 [[TMP24]]
+; CHECK-NEXT: [[WIDE_VEC4:%.*]] = load <16 x i8>, ptr [[TMP25]], align 1
+; CHECK-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <16 x i8> [[WIDE_VEC4]], <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i8> [[STRIDED_VEC5]], i64 7
+; CHECK-NEXT: store i8 [[TMP26]], ptr [[DST]], align 1
+; CHECK-NEXT: [[INDEX_NEXT6]] = add nuw i32 [[INDEX3]], 8
+; CHECK-NEXT: [[TMP27:%.*]] = icmp eq i32 [[INDEX_NEXT6]], [[N_VEC2]]
+; CHECK-NEXT: br i1 [[TMP27]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[VEC_EPILOG_SCALAR_PH]]
+; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL7:%.*]] = phi i32 [ [[TMP21]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP10]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL7]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SADD:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[IV]], i32 0)
+; CHECK-NEXT: [[EV:%.*]] = extractvalue { i32, i1 } [[SADD]], 0
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[SRC]], i32 [[EV]]
+; CHECK-NEXT: [[X:%.*]] = load i8, ptr [[GEP]], align 1
+; CHECK-NEXT: store i8 [[X]], ptr [[DST]], align 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 2
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow(i32 %iv, i32 0)
+ %ev = extractvalue { i32, i1 } %sadd, 0
+ %gep = getelementptr i8, ptr %src, i32 %ev
+ %x = load i8, ptr %gep
+ store i8 %x, ptr %dst
+ %iv.next = add nuw i32 %iv, 2
+ %ec = icmp eq i32 %iv.next, %n
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
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If the struct to extract isn't widened, e.g. because it's fed into an
address computation for an interleave, don't widen the extractvalue. A
single scalar extractvalue can still be executed ok.
Fixes a crash reported in
#219941 (comment)