[DNR] Remove soc specific HPF code

applications/hpf/gpio/src/main.c

@@ -25,45 +25,6 @@
 #define VEVIF_IRQN(vevif) VEVIF_IRQN_1(vevif)
 #define VEVIF_IRQN_1(vevif) VPRCLIC_##vevif##_IRQn
 
-#if defined(CONFIG_SOC_NRF54L15) || defined(CONFIG_SOC_NRF54LM20A) || defined(CONFIG_SOC_NRF54LM20B)
-static const uint8_t pin_to_vio_map[] = {
-	4,  /* Physical pin 0 */
-	0,  /* Physical pin 1 */
-	1,  /* Physical pin 2 */
-	3,  /* Physical pin 3 */
-	2,  /* Physical pin 4 */
-	5,  /* Physical pin 5 */
-	6,  /* Physical pin 6 */
-	7,  /* Physical pin 7 */
-	8,  /* Physical pin 8 */
-	9,  /* Physical pin 9 */
-	10, /* Physical pin 10 */
-};
-
-#define VIO_PORT 2
-#define VIO_PIN_OFFSET 0
-
-#elif defined(CONFIG_SOC_NRF54LV10A)
-static const uint8_t pin_to_vio_map[] = {
-	4,  /* Physical pin 15 */
-	0,  /* Physical pin 16 */
-	1,  /* Physical pin 17 */
-	3,  /* Physical pin 18 */
-	2,  /* Physical pin 19 */
-	5,  /* Physical pin 20 */
-	6,  /* Physical pin 21 */
-	7,  /* Physical pin 22 */
-	8,  /* Physical pin 23 */
-	9,  /* Physical pin 24 */
-};
-
-#define VIO_PORT 1
-#define VIO_PIN_OFFSET 15
-
-#else
-#error "Unsupported target"
-#endif
-
 #define VIO_INDEX_INVALID UINT8_MAX
 #define VIO_PIN_MASK_INVALID UINT16_MAX
 

applications/hpf/mspi/Kconfig

@@ -5,7 +5,7 @@ config HPF_MSPI_MAX_RESPONSE_SIZE
 config HPF_MSPI_IPC_NO_COPY
 	bool "IPC no copy mode"
 	default y
-	depends on SOC_NRF54L15 || SOC_NRF54LM20A || SOC_NRF54LM20B
+	depends on SOC_NRF54L15 || SOC_NRF54LM20A || SOC_NRF54LM20B || SOC_NRF54LV10A
 	help
 	  If y Data is passed through IPC by reference,
 	  this requires both cores to be able to access each others memory spaces.
@@ -18,6 +18,14 @@ config HPF_MSPI_FAULT_TIMER
 	  Timer is used to detect application faults. If the timer expires,
 	  the application is considered to be in a fault state.
 
+config HPF_MSPI_CORRECT_FOR_EXTRA_VTIM_CYCLE
+	bool "HPF MSPI application should take into account an extra clock cycle output by VTIM."
+	default y if SOC_NRF54L15
+	default n
+	help
+	  If enabled, HPF MSPI application corrects for an extra clock cycle generated by VTIM
+	  real-time peripheral.
+
 config HPF_DEVELOPER_MODE
 	bool "HPF developer mode"
 	help

applications/hpf/mspi/README.rst

@@ -9,7 +9,7 @@ High-Performance Framework MSPI
 
 .. caution::
 
-   The High-Performance Framework (HPF) support in the |NCS| is :ref:`experimental <software_maturity>` and is limited to the nRF54L15 and nRF54LM20A/B devices.
+   The High-Performance Framework (HPF) support in the |NCS| is :ref:`experimental <software_maturity>` and is limited to the nRF54L15, nRF54LM20A/B, and nRF54LV10A devices.
 
 This application demonstrates how to write a :ref:`High-Performance Framework (HPF) <hpf_index>` application and communicate with it.
 The application implements a subset of the Zephyr MSPI API.
@@ -361,7 +361,7 @@ The following tests utilize the MSPI driver along with this application:
 * ``nrf/tests/zephyr/drivers/mspi/flash``
 * ``nrf/tests/zephyr/drivers/flash/common``
 
-These tests report results through serial port (the USB debug port on the nRF54L15 or nRF54LM20 DK).
+These tests report results over the serial port, using the USB debug port on the nRF54L15, nRF54LM20, or nRF54LV10 DK.
 
 Dependencies
 ************
@@ -398,3 +398,4 @@ FLPR application HRT
   * :file:`applications/hpf/mspi/src/hrt/hrt-nrf54l15.s`
   * :file:`applications/hpf/mspi/src/hrt/hrt-nrf54lm20a.s`
   * :file:`applications/hpf/mspi/src/hrt/hrt-nrf54lm20b.s`
+  * :file:`applications/hpf/mspi/src/hrt/hrt-nrf54lv10a.s`

applications/hpf/mspi/boards/nrf54lv10dk_nrf54lv10a_cpuflpr.overlay

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		sram_tx: memory@2002b000 {
+			reg = <0x2002b000 0x07f0>;
+		};
+
+		sram_rx: memory@2002b7f0 {
+			reg = <0x2002b7f0 0x07f0>;
+		};
+
+		cpuflpr_error_code: memory@2002bfe0 {
+			reg = <0x2002bfe0 0x0020>; /* 32 bytes */
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuflpr_rram {
+	reg = <0xf9400 DT_SIZE_K(15)>;
+	ranges = <0x0 0xf9400 DT_SIZE_K(15)>;
+};
+
+&cpuflpr_code_partition {
+	reg = <0x0 DT_SIZE_K(15)>;
+};
+
+&cpuflpr_sram {
+	reg = <0x2002c000 DT_SIZE_K(15)>;
+	ranges = <0x0 0x2002c000 0x3c00>;
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+	interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>;
+	nordic,tasks = <1>;
+	nordic,tasks-mask = <0x00010000>;
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "disabled";
+};
+
+&gpiote20 {
+	status = "disabled";
+};
+
+&gpiote30 {
+	status = "disabled";
+};
+
+&grtc {
+	status = "disabled";
+};
+
+&uart20 {
+	status = "disabled";
+};
+
+&uart30 {
+	status = "disabled";
+};

applications/hpf/mspi/sample.yaml

@@ -12,6 +12,7 @@ tests:
       - nrf54l15dk/nrf54l15/cpuflpr
       - nrf54lm20dk/nrf54lm20a/cpuflpr
       - nrf54lm20dk/nrf54lm20b/cpuflpr
+      - nrf54lv10dk/nrf54lv10a/cpuflpr
     tags:
       - ci_build
       - sysbuild