[nrf fromtree] hal_nordic: ironside: Add 9251 peripherals#4099
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| # SPIS120 P5 Mappings | ||
| NrfPsel(fun=NrfFun.SPIS_SCK, port=5, pin=1): Ctrlsel.SERIAL0, | ||
| NrfPsel(fun=NrfFun.SPIS_MOSI, port=5, pin=4): Ctrlsel.SERIAL0, | ||
| NrfPsel(fun=NrfFun.SPIS_MISO, port=5, pin=2): Ctrlsel.SERIAL0, |
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MISO and MOSI might be inverted here
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MISO / MOSI is expected to be swapped between SPI Slave and SPI Master configurations
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| NrfPsel(fun=NrfFun.UART_RTS, port=9, pin=1): Ctrlsel.SERIAL0, | ||
| NrfPsel(fun=NrfFun.UART_RX, port=9, pin=4): Ctrlsel.SERIAL0, | ||
| NrfPsel(fun=NrfFun.UART_TX, port=9, pin=3): Ctrlsel.SERIAL0, | ||
| }, |
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Maybe add TPIU pins for nrf9280 as well?
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| NrfPsel(fun=NrfFun.GRTC_CLKOUT_FAST, port=2, pin=1): Ctrlsel.CAN_TDM_SERIAL2, | ||
| }, | ||
| # Coresight (TPIU) – TDD | ||
| 0xBF04_0000: { |
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Is this base address wrong? @jonathannilsen also wrong in 54H20?
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It is indeed not the TPIU address but the base address of the coresight area. The address matches the node where the pinctrl properties are (the coresight node), see: https://github.com/nrfconnect/sdk-zephyr/blob/main/snippets/nordic/nordic-log-stm-tpiu-dict/boards/nrf54h20_cpuapp.overlay
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- Add Fast peripherals, GRTC CLCK pin, VPR121, VPR130 and MIPIRFFE Ctrlsel configuration to nRF9251. - Add Trace port Ctrlsel support for nRF9251 and nRF9280. - Simplify script by removing Family and rely only on SoC number. (cherry picked from commit 0d744a0cc63b1c49408985be54d4f224673f74c3) Signed-off-by: Aymen LAOUINI <aymen.laouini@nordicsemi.no>
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Add Fast peripherals, GRTC CLCK pin, VPR121, VPR130
and MIPIRFFE Ctrlsel configuration to nRF9251.
Add Trace port Ctrlsel support for nRF9251 and nRF9280.
Simplify script by removing Family and rely only on SoC
number.
(cherry picked from commit zephyrproject-rtos/zephyr@0d744a0)