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221 changes: 221 additions & 0 deletions config/rv64gc/pma.yaml
Original file line number Diff line number Diff line change
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# pma.yaml
# Describes RISC-V Physical Memory Attributes (PMA) for a platform.
# See RISC-V Privileged Architectures specification for more details on PMA.

# Required fields:
# name: A string name for the PMA region.
# lo: The lower bound of the PMA region, as a hexadecimal string.
# hi: The upper bound of the PMA region, as a hexadecimal string.
# attributes: A dictionary of PMA attributes for the region.
# The following attributes are required:
# size: A list of supported access sizes (in bytes) for the region.
# read: A boolean indicating if the region is readable.
# write: A boolean indicating if the region is writable.
# execute: A boolean indicating if the region is executable.
# cacheable: A boolean indicating if the region is cacheable.
# coherent: A boolean indicating if the region is coherent.
# Writes by one agent to an address in the region are eventually visible to other coherent agents in the system.
# The following attributes are optional and have default values if not specified:
# idempotent_read: A boolean indicating if reads from the region are idempotent (default: same as read)
# idempotent_write: A boolean indicating if writes to the region are idempotent (default: same as write)
# hptw_read: A boolean indicating if the region supports host page table walks (default: same as read)
# hptw_write: A boolean indicating if the region supports host page table walks (default: same as write)
# misaligned_scalar: A boolean indicating if the region supports misaligned scalar accesses (default: false)
# misaligned_vector: A boolean indicating if the region supports misaligned vector accesses (default: false)
# cboz: A boolean indicating if the region supports cache block zeroing (default: false)
# ordering: The memory ordering model for the region, as a string (default: "ioweak")
# Options: "MainMem", "IORelaxed", "IOStrongCh0", "IOStrongCh1", "Other"
# amo: The type of atomic memory operations supported by the region, as a string (default: "AMONone")
# Options: "AMONone", "AMOSwap", "AMOLogical", "AMOArithmetic", "AMOCASW", "AMOCASD", "AMOCASQ"
# reserve: The type of reservation granularity for the region, as a string (default: "RsrvNone")
# Options: "RsrvNone", "RsrvNonEventual", "RsrvEventual"
# misaligned_atomicity_granule: The granularity (in bytes) for atomic accesses to the region that support misaligned atomics (default: 0, meaning misaligned AMOs are not supported)
pma_regions:
- name: "BOOTROM"
lo: "0x0000001000"
hi: "0x0000001FFF"
attributes:
size: [1, 2, 4, 8]
read: true
write: false
execute: true
cachable: true
coherent: true
idempotent_read: true
idempotent_write: false
hptw_read: true
hptw_write: false
misaligned_scalar: true
misaligned_vector: true
cboz: false
ordering: MainMem
amo: AMONone
reserve: RsrvNone
misaligned_atomicity_granule: 0
- name: "SDC"
lo: "0x0000012100"
hi: "0x000001211F"
attributes:
size: [4, 8]
read: true
write: true
execute: false
cachable: false
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Copilot AI Feb 13, 2026

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The attribute name should be "cacheable" (not "cachable") to match the documentation on line 15 and maintain consistency with the correct spelling.

Copilot uses AI. Check for mistakes.
coherent: false
idempotent_read: false
idempotent_write: false
hptw_read: false
hptw_write: false
misaligned_scalar: false
misaligned_vector: false
cboz: false
ordering: IOStrongCh0
amo: AMONone
reserve: RsrvNone
misaligned_atomicity_granule: 0
- name: "CLINT"
lo: "0x0002000000"
hi: "0x000200FFFF"
attributes:
size: [1, 2, 4, 8]
read: true
write: true
execute: false
cachable: false
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The attribute name should be "cacheable" (not "cachable") to match the documentation on line 15 and maintain consistency with the correct spelling.

Copilot uses AI. Check for mistakes.
coherent: false
idempotent_read: false
idempotent_write: false
hptw_read: false
hptw_write: false
misaligned_scalar: false
misaligned_vector: false
cboz: false
ordering: IOStrongCh0
amo: AMONone
reserve: RsrvNone
misaligned_atomicity_granule: 0
- name: "PLIC"
lo: "0x000C000000"
hi: "0x000FFFFFFF"
attributes:
size: [4]
read: true
write: true
execute: false
cachable: false
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The attribute name should be "cacheable" (not "cachable") to match the documentation on line 15 and maintain consistency with the correct spelling.

Copilot uses AI. Check for mistakes.
coherent: false
idempotent_read: false
idempotent_write: false
hptw_read: false
hptw_write: false
misaligned_scalar: false
misaligned_vector: false
cboz: false
ordering: IOStrongCh0
amo: AMONone
reserve: RsrvNone
misaligned_atomicity_granule: 0
- name: "UART0"
lo: "0x0010000000"
hi: "0x0010000007"
attributes:
size: [1]
read: true
write: true
execute: false
cachable: false
coherent: false
idempotent_read: false
idempotent_write: false
hptw_read: false
hptw_write: false
misaligned_scalar: false
misaligned_vector: false
cboz: false
ordering: IOStrongCh0
amo: AMONone
reserve: RsrvNone
misaligned_atomicity_granule: 0
- name: "GPIO"
lo: "0x0010060000"
hi: "0x00100600FF"
attributes:
size: [4]
read: true
write: true
execute: false
cachable: false
coherent: false
idempotent_read: false
idempotent_write: false
hptw_read: false
hptw_write: false
misaligned_scalar: false
misaligned_vector: false
cboz: false
ordering: IOStrongCh0
amo: AMONone
reserve: RsrvNone
misaligned_atomicity_granule: 0
- name: "SPI"
lo: "0x0010040000"
hi: "0x0010040FFF"
attributes:
size: [4]
read: true
write: true
execute: false
cachable: false
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The attribute name should be "cacheable" (not "cachable") to match the documentation on line 15 and maintain consistency with the correct spelling.

Copilot uses AI. Check for mistakes.
coherent: false
idempotent_read: false
idempotent_write: false
hptw_read: false
hptw_write: false
misaligned_scalar: false
misaligned_vector: false
cboz: false
ordering: IOStrongCh0
amo: AMONone
reserve: RsrvNone
misaligned_atomicity_granule: 0
- name: "UNCORE_RAM"
lo: "0x0080000000"
hi: "0x008FFFFFFF"
attributes:
size: [1, 2, 4, 8]
read: true
write: true
execute: true
cachable: true
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The attribute name should be "cacheable" (not "cachable") to match the documentation on line 15 and maintain consistency with the correct spelling.

Copilot uses AI. Check for mistakes.
coherent: true
idempotent_read: true
idempotent_write: true
hptw_read: true
hptw_write: true
misaligned_scalar: true
misaligned_vector: true
cboz: true
ordering: MainMem
amo: AMOArithmetic
reserve: RsrvEventual
misaligned_atomicity_granule: 64
- name: "Undefined memory inaccessible"
lo: "0x0000000000"
hi: "0xFFFFFFFFFFFFFFFFFF"
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The hexadecimal value has 18 hex digits, which exceeds the maximum for a 64-bit address (16 hex digits). For rv64gc (64-bit RISC-V), the maximum address should be "0xFFFFFFFFFFFFFFFF" (16 F's, not 18).

Suggested change
hi: "0xFFFFFFFFFFFFFFFFFF"
hi: "0xFFFFFFFFFFFFFFFF"

Copilot uses AI. Check for mistakes.
attributes:
read: false
write: false
execute: false
cachable: false
coherent: false
idempotent_read: false
idempotent_write: false
hptw_read: false
hptw_write: false
misaligned_scalar: false
misaligned_vector: false
cboz: false
ordering: Other
amo: AMONone
reserve: RsrvNone
misaligned_atomicity_granule: 0