[CPU][RV64] Implemented jit_ceil_emitter

src/plugins/intel_cpu/src/emitters/plugin/riscv64/jit_eltwise_emitters.cpp

@@ -119,6 +119,60 @@ std::set<std::vector<element::Type>> jit_add_emitter::get_supported_precisions(
     [[maybe_unused]] const std::shared_ptr<ov::Node>& node) {
     return {{element::f32, element::f32}, {element::i32, element::i32}};
 }
+/// CEIL ///
+jit_ceil_emitter::jit_ceil_emitter(jit_generator_t* host, cpu_isa_t host_isa, const element::Type exec_prc)
+    : jit_emitter(host, host_isa, exec_prc) {
+    prepare_table();
+}
+
+jit_ceil_emitter::jit_ceil_emitter(ov::intel_cpu::riscv64::jit_generator_t* host,
+                                   ov::intel_cpu::riscv64::cpu_isa_t host_isa,
+                                   const std::shared_ptr<ov::Node>& node)
+    : jit_emitter(host, host_isa, get_arithmetic_binary_exec_precision(node)) {
+    prepare_table();
+}
+
+size_t jit_ceil_emitter::get_inputs_num() const {
+    return 1;
+}
+
+size_t jit_ceil_emitter::aux_fp_gprs_count() const {
+    return 1;
+}
+
+void jit_ceil_emitter::emit_impl(const std::vector<size_t>& in_vec_idxs,
+                                 const std::vector<size_t>& out_vec_idxs) const {
+    if (host_isa_ == ov::intel_cpu::riscv64::cpu_isa_t::gv) {
+        emit_isa<ov::intel_cpu::riscv64::cpu_isa_t::gv>(in_vec_idxs, out_vec_idxs);
+    } else {
+        OV_CPU_JIT_EMITTER_THROW("Can't create jit eltwise kernel for CEIL");
+    }
+}
+
+void jit_ceil_emitter::register_table_entries() {
+    push_arg_entry_of("one", 0x3f800000);
+}
+
+template <ov::intel_cpu::riscv64::cpu_isa_t isa>
+void jit_ceil_emitter::emit_isa(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const {
+    OV_CPU_JIT_EMITTER_ASSERT(exec_prc_ == ov::element::f32, "Unsupported precision: ", exec_prc_);
+
+    auto src = VReg(in_vec_idxs[0]);
+    auto dst = VReg(out_vec_idxs[0]);
+    auto fp1 = FReg(aux_fp_gpr_idxs[0]);
+
+    h->vfcvt_x_f_v(dst, src);
+    h->vfcvt_f_x_v(dst, dst);
+
+    h->vmflt_vv(mask_vreg(), dst, src);
+    load_table_val("one", fp1);
+    h->vfadd_vf(dst, dst, fp1, VM::masked);
+}
+
+std::set<std::vector<element::Type>> jit_ceil_emitter::get_supported_precisions(
+    [[maybe_unused]] const std::shared_ptr<ov::Node>& node) {
+    return {{element::f32}};
+}
 
 /// Clamp ///
 jit_clamp_emitter::jit_clamp_emitter(ov::intel_cpu::riscv64::jit_generator_t* host,

src/plugins/intel_cpu/src/emitters/plugin/riscv64/jit_eltwise_emitters.hpp

@@ -50,7 +50,26 @@ class jit_add_emitter : public jit_emitter {
     template <ov::intel_cpu::riscv64::cpu_isa_t isa>
     void emit_isa(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const;
 };
+class jit_ceil_emitter : public jit_emitter {
+public:
+    jit_ceil_emitter(jit_generator_t* host, cpu_isa_t host_isa, element::Type exec_prc = element::f32);
+
+    jit_ceil_emitter(jit_generator_t* host, cpu_isa_t host_isa, const std::shared_ptr<ov::Node>& node);
+
+    size_t get_inputs_num() const override;
+    size_t aux_fp_gprs_count() const override;
+
+    static std::set<std::vector<element::Type>> get_supported_precisions(
+        const std::shared_ptr<ov::Node>& node = nullptr);
 
+private:
+    void emit_impl(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const override;
+
+    template <cpu_isa_t isa>
+    void emit_isa(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const;
+
+    void register_table_entries() override;
+};
 class jit_clamp_emitter : public jit_emitter {
 public:
     jit_clamp_emitter(ov::intel_cpu::riscv64::jit_generator_t* host,

src/plugins/intel_cpu/src/nodes/executors/jit/eltwise.cpp

@@ -443,6 +443,7 @@ bool EltwiseJitExecutor::supports(const EltwiseAttrs& attrs,
     if (!any_of(algorithm,
                 Algorithm::EltwiseAbs,
                 Algorithm::EltwiseAdd,
+                Algorithm::EltwiseCeiling,
                 Algorithm::EltwiseClamp,
                 Algorithm::EltwiseDivide,
                 Algorithm::EltwiseElu,

src/plugins/intel_cpu/src/nodes/kernels/riscv64/jit_uni_eltwise_generic.cpp

@@ -483,6 +483,7 @@ std::shared_ptr<jit_emitter> jit_uni_eltwise_generic<isa>::create_eltwise_emitte
               data.algo,
               OV_CASE(Algorithm::EltwiseAbs, jit_abs_emitter),
               OV_CASE(Algorithm::EltwiseAdd, jit_add_emitter),
+              OV_CASE(Algorithm::EltwiseCeiling, jit_ceil_emitter),
               OV_CASE(Algorithm::EltwiseClamp, jit_clamp_emitter),
               OV_CASE(Algorithm::EltwiseDivide, jit_divide_emitter),
               OV_CASE(Algorithm::EltwiseElu, jit_elu_emitter),
@@ -643,6 +644,7 @@ std::set<std::vector<element::Type>> eltwise_precision_helper::get_supported_pre
               algo,
               OV_CASE(Algorithm::EltwiseAbs, jit_abs_emitter),
               OV_CASE(Algorithm::EltwiseAdd, jit_add_emitter),
+              OV_CASE(Algorithm::EltwiseCeiling, jit_ceil_emitter),
               OV_CASE(Algorithm::EltwiseClamp, jit_clamp_emitter),
               OV_CASE(Algorithm::EltwiseDivide, jit_divide_emitter),
               OV_CASE(Algorithm::EltwiseElu, jit_elu_emitter),

src/plugins/intel_cpu/tests/functional/custom/single_layer_tests/classes/activation.cpp

@@ -225,6 +225,7 @@ std::string ActivationLayerCPUTest::getPrimitiveType(const utils::ActivationType
 #if defined(OPENVINO_ARCH_RISCV64)
     if (ov::intel_cpu::riscv64::mayiuse(ov::intel_cpu::riscv64::gv)) {
         if ((activation_type == utils::ActivationTypes::Abs) ||
+            (activation_type == utils::ActivationTypes::Ceiling) ||
             (activation_type == utils::ActivationTypes::Clamp) ||
             (activation_type == utils::ActivationTypes::Elu) ||
             (activation_type == utils::ActivationTypes::Erf) ||