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    • ai4org

      Public
      Python
      0100Updated Oct 23, 2025Oct 23, 2025
    • 1400Updated Oct 20, 2025Oct 20, 2025
    • An All in one RISC-V Suite.
      JavaScript
      3500Updated Oct 10, 2025Oct 10, 2025
    • XSoC-Lite

      Public
      Modular eXtensible SoC (RV32IMCF + BabyKyber accelerator)
      C++
      0000Updated Oct 8, 2025Oct 8, 2025
    • vaquita

      Public
      Scala
      51801Updated Oct 6, 2025Oct 6, 2025
    • Python
      1000Updated Sep 28, 2025Sep 28, 2025
    • XSoC-SDK

      Public
      SDK for Modular eXtensible SoC
      C
      1000Updated Sep 27, 2025Sep 27, 2025
    • nucleusrv

      Public
      NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
      Assembly
      3475133Updated Sep 21, 2025Sep 21, 2025
    • Shell
      2100Updated Sep 21, 2025Sep 21, 2025
    • genify

      Public
      Jupyter Notebook
      0000Updated Sep 15, 2025Sep 15, 2025
    • riscv-dv

      Public
      Random instruction generator for RISC-V processor verification
      Python
      356001Updated Sep 7, 2025Sep 7, 2025
    • This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks related to it.
      Jupyter Notebook
      741400Updated Sep 7, 2025Sep 7, 2025
    • An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      Scala
      773001Updated Aug 31, 2025Aug 31, 2025
    • oxygen

      Public
      A RISC-V Simulator
      Python
      3600Updated Aug 29, 2025Aug 29, 2025
    • Athestia

      Public
      Clean slate application using NDN with Dilithium to enhance security in future internet technology
      0300Updated Aug 27, 2025Aug 27, 2025
    • autovar

      Public
      0001Updated Aug 27, 2025Aug 27, 2025
    • hammer

      Public
      Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
      C++
      9200Updated Aug 26, 2025Aug 26, 2025
    • coco-rvtb

      Public
      Generic testbench for RISC-V CPUs
      Python
      8711Updated Aug 25, 2025Aug 25, 2025
    • Chisel generator based on OpenTCAM, to be used w. merledu/pristine-chipyard
      SystemVerilog
      1000Updated Aug 23, 2025Aug 23, 2025
    • LFX Mentorship: Projects and Coding Challenges
      57201Updated Jul 25, 2025Jul 25, 2025
    • SHA3-256

      Public
      SystemVerilog
      0000Updated Jun 25, 2025Jun 25, 2025
    • A Kyber768-90's Hardware Accelerator.
      SystemVerilog
      3400Updated Jun 15, 2025Jun 15, 2025
    • aegis

      Public
      1001Updated May 14, 2025May 14, 2025
    • An open source Mini SoC Generator which will generate SoC based on parameters.
      Verilog
      1381Updated Mar 25, 2025Mar 25, 2025
    • caravan

      Public
      A caravan equipped with API for creating bus protocols in Chisel with ease.
      Scala
      121440Updated Mar 22, 2025Mar 22, 2025
    • Project ideas list for Google Summer of Code.
      21600Updated Feb 10, 2025Feb 10, 2025
    • Python
      0000Updated Feb 2, 2025Feb 2, 2025
    • JavaScript
      0000Updated Feb 2, 2025Feb 2, 2025
    • Jupyter Notebook
      1000Updated Dec 26, 2024Dec 26, 2024
    • Python
      0000Updated Dec 2, 2024Dec 2, 2024