Support for Cadence Xcelium simulator #193
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micprog
requested changes
Mar 31, 2025
src/script_fmt/xm_sh.tera
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| {% endif %} | ||
| ROOT="{{ root }}" | ||
| {% for group in srcs %} | ||
| {% if group.file_type == 'verilog' %}xmvlog -sv \ |
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I see you have support for verilog files, which is a great start. As bender is generally built to support vhdl files as well, and this simulator supports vhdl, it would be great to ensure compatibility here as well.
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We don't have any VHDL code internally to test with. If there is a public Bender repo with VHDL code and a simulation target, please refer me to it an I'll try to include the template.
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Adds basic support for Cadence Xcelium simulator.
Only verilog (not vhdl) tested.