[rl] Add XPU support to upstream GRPO training pipeline#3890
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Enable the full GRPO RL pipeline (trainer + vLLM generator) to run on Intel XPU alongside CUDA with minimal, config-driven changes. Key changes: 1. Device detection via ZE_AFFINITY_MASK (always present on Intel GPU systems) -- no runtime torch.xpu.is_available() checks needed. 2. expandable_segments guard: PYTORCH_CUDA_ALLOC_CONF is only set when ZE_AFFINITY_MASK is absent. On XPU the CUDA allocator config corrupts oneDNN USM pointers, causing oneCCL collective failures. 3. Bootstrap callable in PerHostProvisioner sets ZE_AFFINITY_MASK (XPU) or CUDA_VISIBLE_DEVICES (CUDA) inside the child process before Level Zero / CUDA runtime initialization. 4. Generator attention_config field using vLLM's AttentionConfig type. Default (None) preserves existing behavior; XPU config passes AttentionConfig() to let vLLM's platform auto-select the backend. 5. decoder.py: gate separate_full_blocks kwarg on inspect.signature for PyTorch version compatibility. 6. XPU config in config_registry.py: disable max_autotune (avoids OUT_OF_RESOURCES on backward), override FlexAttention class var. 7. Remove xpu_compat.py monkey-patching in favor of the above. Files changed: - torchtitan/models/common/decoder.py (version compat, no behavior change) - torchtitan/experiments/rl/__init__.py (ZE_AFFINITY_MASK guard, lazy imports) - torchtitan/experiments/rl/train.py (bootstrap callable, XPU guards) - torchtitan/experiments/rl/actors/generator.py (attention_config field) - torchtitan/experiments/rl/actors/trainer.py (remove apply_patches) - torchtitan/experiments/rl/examples/alphabet_sort/config_registry.py (XPU config) Verified: 10-step GRPO on 4x Intel Max 1550, reward 0.194 -> 0.351.
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Summary
Enable the full GRPO RL pipeline (trainer + vLLM generator + TorchStore weight sync) to run on Intel XPU via the standard
train.pyentry point, with no changes to core torchtitan code.Changes
rl/__init__.py: GuardPYTORCH_CUDA_ALLOC_CONF=expandable_segments:TruebehindPYTORCH_XPU_ALLOC_CONFcheck. On XPU,expandable_segmentscorrupts the oneDNN memory allocator's USM pointers, breaking all oneCCL collectives. Also makes vLLM imports lazy to preventvllm_xpu_kernelsC extensions from initializing a SYCL context in the trainer process.actors/generator.py: Auto-select the vLLM attention backend on XPU. vLLM's XPU platform only supportsFLASH_ATTNandTRITON_ATTN; passingFLEX_ATTENTIONraisesValueError. Settingbackend=Nonelets vLLM default toflash_attnon XPU.actors/trainer.py: Apply XPU compatibility patches on init.xpu_compat.py(new): XPU-specific monkey-patches that are idempotent no-ops on CUDA:max_autotune(avoidsOUT_OF_RESOURCESon backward autotuning)FORCE_USE_FLEX_ATTENTIONkernel option (flex_decoding crashes on Q_LEN < 128)separate_full_blockskwarg fromcreate_block_masktrain.py: Bootstrap callable setsZE_AFFINITY_MASKfor XPU device isolation (detected via inherited env from launcher).config_registry.py: Addrl_grpo_lora_qwen3_0_6bconfig using FSDP (dp_shard=2) + LoRA that works on both CUDA and XPU.run_grpo_lora_xpu.sh: Example launcher script for Intel XPU.Test plan
python3 -m torchtitan.experiments.rl.train --module alphabet_sort --config rl_grpo_lora_qwen3_0_6btorch.xpu.is_available()or env var checks)