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Add Zilsd/Zclsd Support
Co-authored-by: Simona Costinescu <[email protected]>
1 parent 1057974 commit 179b3be

8 files changed

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-1
lines changed

‎README.md

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@@ -126,6 +126,7 @@ Supported RISC-V ISA features
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- Svinval extension for fine-grained address-translation cache invalidation, v1.0
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- Sv32, Sv39, Sv48 and Sv57 page-based virtual-memory systems
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- Physical Memory Protection (PMP)
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- Zilsd and Zclsd extensions for RV32 Load/Store pair instructions, v1.0
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**For a list of unsupported extensions and features, see the [Extension Roadmap](https://github.com/riscv/sail-riscv/wiki/Extension-Roadmap).**
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‎config/default.json

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@@ -68,6 +68,12 @@
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"Zicboz" : {
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"enabled" : false
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},
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"Zilsd": {
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"enabled": true
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},
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"Zclsd": {
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"enabled": true
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},
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"Zvkb" : {
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"enabled" : false
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},

‎model/CMakeLists.txt

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@@ -78,6 +78,8 @@ foreach (xlen IN ITEMS 32 64)
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${vext_srcs}
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"riscv_insts_zicbom.sail"
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"riscv_insts_zicboz.sail"
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"riscv_insts_zilsd.sail"
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"riscv_insts_zclsd.sail"
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"riscv_insts_zvbb.sail"
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"riscv_insts_zvbc.sail"
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# Zimop and Zcmop should be at the end so they can be overridden by earlier extensions

‎model/riscv_insts_zcf.sail

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@@ -15,7 +15,7 @@
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/* ****************************************************************** */
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function clause extensionEnabled(Ext_Zcf) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_F) & xlen == 32
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function clause extensionEnabled(Ext_Zcf) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_F) & not(sys_enable_zclsd()) & (xlen == 32)
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union clause ast = C_FLWSP : (bits(6), fregidx)
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‎model/riscv_insts_zclsd.sail

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/*=======================================================================================*/
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/* This Sail RISC-V architecture model, comprising all files and */
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/* directories except where otherwise noted is subject the BSD */
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/* two-clause license in the LICENSE file. */
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/* */
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*=======================================================================================*/
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function clause extensionEnabled(Ext_Zclsd) = true & sys_enable_zilsd() & extensionEnabled(Ext_Zca) & not(extensionEnabled(Ext_Zcf)) & xlen == 32
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/* ****************************************************************** */
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union clause ast = ZCLSD_C_LDSP : (bits(9), regidx)
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mapping clause encdec_compressed = ZCLSD_C_LDSP(ui86 @ ui5 @ ui43 @ 0b000, rd)
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<-> 0b011 @ ui5 : bits(1) @ encdec_reg(rd) @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10
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when extensionEnabled(Ext_Zclsd)
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function clause execute (ZCLSD_C_LDSP(imm, rd)) = {
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execute(ZILSD_LD(zero_extend(imm), sp, rd))
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}
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mapping clause assembly = ZCLSD_C_LDSP(uimm, rd)
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<-> "c.ldsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_9(uimm)
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when xlen == 32
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/* ****************************************************************** */
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union clause ast = ZCLSD_C_SDSP : (bits(9), regidx)
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mapping clause encdec_compressed = ZCLSD_C_SDSP(ui86 @ ui53 @ 0b000, rs2)
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<-> 0b111 @ ui53 : bits(3) @ ui86 : bits(3) @ encdec_reg(rs2) @ 0b10
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when extensionEnabled(Ext_Zclsd)
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function clause execute (ZCLSD_C_SDSP(uimm, rs2)) = {
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execute(ZILSD_SD(zero_extend(uimm), rs2, sp))
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}
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mapping clause assembly = ZCLSD_C_SDSP(uimm, rs2)
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<-> "c.sdsp" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_9(uimm)
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when xlen == 32
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/* ****************************************************************** */
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union clause ast = ZCLSD_C_LD : (bits(8), cregidx, cregidx)
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mapping clause encdec_compressed = ZCLSD_C_LD(ui76 @ ui53 @ 0b000, rs1, rd)
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<-> 0b011 @ ui53 : bits(3) @ encdec_creg(rs1) @ ui76 : bits(2) @ encdec_creg(rd) @ 0b00
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when extensionEnabled(Ext_Zclsd)
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function clause execute (ZCLSD_C_LD(uimm, rsc, rdc)) = {
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let rd = creg2reg_idx(rdc);
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let rs = creg2reg_idx(rsc);
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execute(ZILSD_LD(zero_extend(uimm), rs, rd))
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}
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mapping clause assembly = ZCLSD_C_LD(uimm, rsc, rdc)
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<-> "c.ld" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_8(uimm)
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when xlen == 32
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/* ****************************************************************** */
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union clause ast = ZCLSD_C_SD : (bits(8), cregidx, cregidx)
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mapping clause encdec_compressed = ZCLSD_C_SD(ui76 @ ui53 @ 0b000, rs1, rs2)
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<-> 0b111 @ ui53 : bits(3) @ encdec_creg(rs1) @ ui76 : bits(2) @ encdec_creg(rs2) @ 0b00
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when extensionEnabled(Ext_Zclsd)
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function clause execute (ZCLSD_C_SD(uimm, rsc1, rsc2)) = {
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let rs1 = creg2reg_idx(rsc1);
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let rs2 = creg2reg_idx(rsc2);
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execute(ZILSD_SD(zero_extend(uimm), rs2, rs1))
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}
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mapping clause assembly = ZCLSD_C_SD(uimm, rsc1, rsc2)
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<-> "c.sd" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_8(uimm)
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when xlen == 32

‎model/riscv_insts_zilsd.sail

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/*=======================================================================================*/
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/* This Sail RISC-V architecture model, comprising all files and */
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/* directories except where otherwise noted is subject the BSD */
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/* two-clause license in the LICENSE file. */
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/* */
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*=======================================================================================*/
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function clause extensionEnabled(Ext_Zilsd) = sys_enable_zilsd() & xlen == 32
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/* ****************************************************************** */
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union clause ast = ZILSD_LD : (bits(12), regidx, regidx)
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mapping clause encdec = ZILSD_LD(imm, rs1, rd)
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<-> imm @ encdec_reg(rs1) @ 0b011 @ encdec_reg(rd) @ 0b0000011
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when extensionEnabled(Ext_Zilsd) & not(bit_to_bool(encdec_reg(rd)[0]))
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function load_imm(imm : bits(12), base_val : xlenbits, rd : regidx, width : word_width) -> Retired = {
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let offset : xlenbits = sign_extend(imm);
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let width_bytes = size_bytes(width);
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assert(width_bytes <= xlen_bytes);
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let vaddr = Virtaddr(base_val + offset);
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if check_misaligned(vaddr, width)
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then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
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else match translateAddr(vaddr, Read(Data)) {
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TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
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TR_Address(paddr, _) => {
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match mem_read(Read(Data), paddr, width_bytes, false, false, false) {
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Ok(result) => { X(rd) = extend_value(false, result); RETIRE_SUCCESS },
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Err(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
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}
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},
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}
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}
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function clause execute ZILSD_LD(imm, rs1, rd) = {
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if rd != zreg then {
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let base_val = X(rs1);
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let _ = load_imm(imm, base_val, rd, WORD);
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load_imm(imm+4, base_val, rd+1, WORD)
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} else {
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RETIRE_SUCCESS
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}
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}
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mapping clause assembly = ZILSD_LD(imm, rs1, rd) <-> "ld" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_signed_12(imm) ^ "(" ^ reg_name(rs1) ^ ")"
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/* ****************************************************************** */
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union clause ast = ZILSD_SD : (bits(12), regidx, regidx)
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mapping clause encdec = ZILSD_SD(imm7 @ imm5, rs2, rs1)
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<-> imm7 : bits(7) @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b011 @ imm5 : bits(5) @ 0b0100011
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when extensionEnabled(Ext_Zilsd) & not(bit_to_bool(encdec_reg(rs2)[0]))
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function store_imm(imm : bits(12), rs2_val : xlenbits, base_val : xlenbits, width : word_width) -> Retired = {
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let offset : xlenbits = sign_extend(imm);
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let width_bytes = size_bytes(width);
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assert(width_bytes <= xlen_bytes);
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let vaddr = Virtaddr(base_val + offset);
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if check_misaligned(vaddr, width)
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then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }
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else match translateAddr(vaddr, Write(Data)) {
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TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
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TR_Address(paddr, _) => {
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match mem_write_ea(paddr, width_bytes, false, false, false) {
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Err(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
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Ok(_) => {
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match mem_write_value(paddr, width_bytes, rs2_val[width_bytes * 8 - 1 .. 0], false, false, false) {
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Ok(true) => RETIRE_SUCCESS,
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Ok(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"),
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Err(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }
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}
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}
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}
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}
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}
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}
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function clause execute ZILSD_SD(imm, rs2, rs1) = {
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let base_val = X(rs1);
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let rs2_val = X(rs2);
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let rs2_pair_val = if rs2 != zreg then X(rs2+1) else rs2_val;
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let _ = store_imm(imm, rs2_val, base_val, WORD);
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store_imm(imm+4, rs2_pair_val, base_val, WORD)
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}
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mapping clause assembly = ZILSD_SD(offset, rs2, rs1) <-> "sd" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_signed_12(offset) ^ "(" ^ reg_name(rs1) ^ ")"

‎model/riscv_sys_regs.sail

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@@ -125,6 +125,10 @@ function sys_enable_bext() -> bool = config extensions.B.enabled
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function sys_enable_zicbom() -> bool = config extensions.Zicbom.enabled
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function sys_enable_zicboz() -> bool = config extensions.Zicboz.enabled
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// "Zilsd", "Zclsd" Extensions for Load/Store pair for RV32
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function sys_enable_zilsd() -> bool = config extensions.Zilsd.enabled
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function sys_enable_zclsd() -> bool = config extensions.Zclsd.enabled
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// Is the Zvkb extension supported.
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function sys_enable_zvkb() -> bool = config extensions.Zvkb.enabled
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‎model/riscv_types.sail

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@@ -37,6 +37,9 @@ newtype regidx = Regidx : bits(5) /* uncompressed register identifiers */
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newtype cregidx = Cregidx : bits(3) /* identifiers in RVC instructions */
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type csreg = bits(12) /* CSR addressing */
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function add_regidx_int(Regidx(reg) : regidx, offset : int) -> regidx = Regidx(reg + offset)
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overload operator + = { add_regidx_int }
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function regidx_offset(Regidx(r) : regidx, o : bits(5)) -> regidx = Regidx(r + o)
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function regidx_bits (Regidx(b) : regidx) -> bits(5) = b
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