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Allow configuring mtvec/stvec MODE as fixed (single-mode) and its reset value

Status: Open.

#1729 In riscv/sail-riscv;

· karabambus opened on May 28, 2026

Allow for read only 0 FS and VS bits in mstatus

configurationAdditional configuration settings needed for the modelAdditional configuration settings needed for the model

Status: Open.

#1722 In riscv/sail-riscv;

· qbojj opened on May 21, 2026

Max Index EEW Parameter Request

configurationAdditional configuration settings needed for the modelAdditional configuration settings needed for the model

vectorIssues related to the Vector extensionIssues related to the Vector extension

Status: Open.

#1719 In riscv/sail-riscv;

· jacassidy opened on May 15, 2026

Segment vector stores may double-write to non-idempotent memory on fault resumption

vectorIssues related to the Vector extensionIssues related to the Vector extension

Status: Open.

#1713 In riscv/sail-riscv;

· nadime15 opened on May 13, 2026

vid.v: vs2 ≠ v0 not explicitly checked in execute

configurationAdditional configuration settings needed for the modelAdditional configuration settings needed for the model

vectorIssues related to the Vector extensionIssues related to the Vector extension

Status: Open.

#1702 In riscv/sail-riscv;

· nadime15 opened on May 8, 2026

Add configuration parameter for vsetvli/vsetvl behavior on reserved vtype values

configurationAdditional configuration settings needed for the modelAdditional configuration settings needed for the model

vectorIssues related to the Vector extensionIssues related to the Vector extension

Status: Open.

#1699 In riscv/sail-riscv;

· UmerShahidengr opened on May 7, 2026

vrgatherei16.vv allowing reserved behavior vs1=vs2 at SEW=32/64

vectorIssues related to the Vector extensionIssues related to the Vector extension

Status: Open.

#1687 In riscv/sail-riscv;

· georgiatai opened on Apr 29, 2026

Add parameter UDB_LRSC_FAIL_ON_NON_EXACT_LRSC for Za64rs support in other simulators.

Status: Open.

#1677 In riscv/sail-riscv;

· Ammarahwakeel opened on Apr 24, 2026

Hardware A/D update unconditional when neither Svadu nor Svade implemented

Status: Open.

#1670 In riscv/sail-riscv;

· nadime15 opened on Apr 21, 2026

Reviewing use of currentlyEnabled vs hartSupports

Status: Open.

#1650 In riscv/sail-riscv;

· pmundkur opened on Apr 6, 2026

Compilation of master with opam fails

Status: Open.

#1618 In riscv/sail-riscv;

· eponier opened on Mar 17, 2026

Config option needed for PMP behavior on misaligned accesses that cross region boundaries

Status: Open.

#1614 In riscv/sail-riscv;

· UmerShahidengr opened on Mar 13, 2026