Change XLEN and FLEN to be configure-time options

This means you only need to compile the emulator once in order to support RV32F, RV32D, RV64F and RV64D.

Author: Timmmm

CMakeLists.txt

@@ -125,8 +125,6 @@ execute_process(
 )
 message(STATUS "Sail library directory: ${sail_dir}")
 
-set(DEFAULT_ARCHITECTURES "rv32d;rv64d" CACHE STRING "Architectures to build by default (rv32f|rv64f|rv32d|rv64d)(_rvfi)? " )
-
 option(COVERAGE "Compile with Sail coverage collection enabled.")
 
 # Softfloat support.
@@ -167,8 +165,8 @@ endif()
 include(CPack)
 
 # Convenience targets.
-add_custom_target(csim DEPENDS riscv_sim_rv32d riscv_sim_rv64d)
-add_custom_target(check DEPENDS generated_model_rv32d generated_model_rv64d)
+add_custom_target(csim DEPENDS riscv_sim_rv)
+add_custom_target(check DEPENDS generated_model_rv)
 
 # TODO: Add `interpret` target.
 # TODO: Add hol4 target.

README.md

@@ -34,16 +34,14 @@ Install [Sail](https://github.com/rems-project/sail/). On Linux you can download
 $ ./build_simulators.sh
 ```
 
-will build the simulators in `build/c_emulator/riscv_sim_rv{32,64}d`.
+will build the simulator at `build/c_emulator/riscv_sim_rv`.
 
 If you get an error message saying `sail: unknown option '--require-version'.` it's because your Sail compiler is too old. You need version 0.19 or later.
 
-By default the RV32D and RV64D emulators are built, without RVFI-DII support.
-You can see a complete list of targets by running `make help` in the
-build directory, then e.g.
+By default the emulator is built without RVFI-DII support. For RVFI support run
 
 ```
-$ make -C build riscv_sim_rv64f_rvfi
+$ make -C build riscv_sim_rv_rvfi
 ```
 
 By default `build_simulators.sh` will download and build [libgmp](https://gmplib.org/).
@@ -54,7 +52,7 @@ To use a system installation of libgmp, run `env DOWNLOAD_GMP=FALSE ./build_simu
 The simulator can be used to execute small test binaries.
 
 ```
-$ build/c_emulator/riscv_sim_<arch> <elf-file>
+$ build/c_emulator/riscv_sim_rv <elf-file>
 ```
 
 A suite of RV32 and RV64 test programs derived from the
@@ -66,13 +64,13 @@ can be run using `make test` or `ctest` in the build directory.
 
 The model is configured using a JSON file specifying various tunable
 options. The default configuration used for the model can be examined
-using `build/c_emulator/riscv_sim_<arch> --print-default-config`. To
+using `build/c_emulator/riscv_sim_rv --print-default-config`. To
 use a custom configuration, save the default configuration into a
 file, edit it as needed, and pass it to the simulator using the
 `--config` option.
 
 Information on other options for the simulator is available from
-`build/c_emulator/riscv_sim_<arch> -h`.
+`build/c_emulator/riscv_sim_rv -h`.
 
 ### Booting OS images
 

c_emulator/CMakeLists.txt

@@ -14,70 +14,57 @@ set(EMULATOR_COMMON_SRCS
     riscv_softfloat.h
 )
 
-foreach (xlen IN ITEMS 32 64)
-    foreach (flen IN ITEMS 32 64)
-        foreach (variant IN ITEMS "" "rvfi")
-            set(arch "rv${xlen}")
-            if (flen EQUAL 32)
-                string(APPEND arch "f")
-            else()
-                string(APPEND arch "d")
-            endif()
-            if (variant)
-                string(APPEND arch "_${variant}")
-            endif()
+foreach (variant IN ITEMS "" "rvfi")
+    set(arch "rv")
+    if (variant)
+        string(APPEND arch "_${variant}")
+    endif()
 
-            add_executable(riscv_sim_${arch}
-                "${CMAKE_BINARY_DIR}/riscv_model_${arch}.c"
-                ${EMULATOR_COMMON_SRCS}
-            )
-            # The generated model is not warnings-clean, silence them.
-            # -Wno-self-assing is needed for `zhtif_tohost = zhtif_tohost`
-            # generated by the sail code to avoid optimizing the function out.
-            set(_generated_c_warning_opt_out
-                -Wno-extra
-                -Wno-unused
-                -Wno-uninitialized
-                $<$<BOOL:${HAVE_WSELF_ASSIGN}>:-Wno-self-assign>
-            )
-            set_source_files_properties("${CMAKE_BINARY_DIR}/riscv_model_${arch}.c"
-                                        PROPERTIES COMPILE_OPTIONS "${_generated_c_warning_opt_out}")
+    add_executable(riscv_sim_${arch}
+        "${CMAKE_BINARY_DIR}/riscv_model_${arch}.c"
+        ${EMULATOR_COMMON_SRCS}
+    )
+    # The generated model is not warnings-clean, silence them.
+    # -Wno-self-assing is needed for `zhtif_tohost = zhtif_tohost`
+    # generated by the sail code to avoid optimizing the function out.
+    set(_generated_c_warning_opt_out
+        -Wno-extra
+        -Wno-unused
+        -Wno-uninitialized
+        $<$<BOOL:${HAVE_WSELF_ASSIGN}>:-Wno-self-assign>
+    )
+    set_source_files_properties("${CMAKE_BINARY_DIR}/riscv_model_${arch}.c"
+                                PROPERTIES COMPILE_OPTIONS "${_generated_c_warning_opt_out}")
 
-            if (NOT arch IN_LIST DEFAULT_ARCHITECTURES)
-                set_target_properties(riscv_sim_${arch} PROPERTIES EXCLUDE_FROM_ALL TRUE)
-            endif()
+    add_dependencies(riscv_sim_${arch} generated_model_${arch})
 
-            add_dependencies(riscv_sim_${arch} generated_model_${arch})
+    target_link_libraries(riscv_sim_${arch}
+        PRIVATE softfloat sail_runtime default_config GMP::GMP
+    )
 
-            target_link_libraries(riscv_sim_${arch}
-                PRIVATE softfloat sail_runtime default_config GMP::GMP
-            )
+    target_include_directories(riscv_sim_${arch}
+        # So the generated C can find riscv_platform/prelude.h"
+        PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}"
+    )
 
-            target_include_directories(riscv_sim_${arch}
-                # So the generated C can find riscv_platform/prelude.h"
-                PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}"
-            )
+    if (arch MATCHES "rvfi")
+        target_compile_definitions(riscv_sim_${arch}
+            PRIVATE RVFI_DII
+        )
+    endif()
 
-            if (arch MATCHES "rvfi")
-                target_compile_definitions(riscv_sim_${arch}
-                    PRIVATE RVFI_DII
-                )
-            endif()
+    # TODO: Enable warnings when we use the #include trick
+    # to include the generated Sail code. Currently it
+    # generates too many warnings to turn these on globally.
 
-            # TODO: Enable warnings when we use the #include trick
-            # to include the generated Sail code. Currently it
-            # generates too many warnings to turn these on globally.
+    # target_compile_options(riscv_sim_${arch} PRIVATE
+    #     -Wall -Wextra
+    #     # Too annoying at the moment.
+    #     -Wno-unused-parameter
+    # )
 
-            # target_compile_options(riscv_sim_${arch} PRIVATE
-            #     -Wall -Wextra
-            #     # Too annoying at the moment.
-            #     -Wno-unused-parameter
-            # )
-
-            install(TARGETS riscv_sim_${arch}
-                OPTIONAL
-                RUNTIME DESTINATION "bin"
-            )
-        endforeach()
-    endforeach()
+    install(TARGETS riscv_sim_${arch}
+        OPTIONAL
+        RUNTIME DESTINATION "bin"
+    )
 endforeach()

c_emulator/riscv_platform.cpp

@@ -24,9 +24,9 @@ mach_bits plat_get_16_random_bits(unit)
   return rv_16_random_bits();
 }
 
-unit load_reservation(mach_bits addr)
+unit load_reservation(sbits addr)
 {
-  reservation = addr;
+  reservation = addr.bits;
   reservation_valid = true;
   RESERVATION_DBG("reservation <- %0" PRIx64 "\n", reservation);
   return UNIT;
@@ -42,10 +42,10 @@ static mach_bits check_mask()
   return (zxlen_val == 32) ? 0x00000000FFFFFFFF : -1;
 }
 
-bool match_reservation(mach_bits addr)
+bool match_reservation(sbits addr)
 {
   mach_bits mask = check_mask();
-  bool ret = reservation_valid && (reservation & mask) == (addr & mask);
+  bool ret = reservation_valid && (reservation & mask) == (addr.bits & mask);
   RESERVATION_DBG("reservation(%c): %0" PRIx64 ", key=%0" PRIx64 ": %s\n",
                   reservation_valid ? 'v' : 'i', reservation, addr,
                   ret ? "ok" : "fail");

c_emulator/riscv_platform.h

@@ -9,8 +9,8 @@ extern "C" {
 mach_bits plat_get_16_random_bits(unit);
 
 bool speculate_conditional(unit);
-unit load_reservation(mach_bits);
-bool match_reservation(mach_bits);
+unit load_reservation(sbits);
+bool match_reservation(sbits);
 unit cancel_reservation(unit);
 
 unit plat_term_write(mach_bits);

c_emulator/riscv_sail.h

@@ -8,12 +8,6 @@ extern "C" {
 
 typedef int unit;
 #define UNIT 0
-typedef uint64_t mach_bits;
-
-struct zMisa {
-  mach_bits zMisa_chunk_0;
-};
-extern struct zMisa zmisa;
 
 void model_init(void);
 void model_fini(void);
@@ -24,9 +18,9 @@ unit ztick_clock(unit);
 unit ztick_platform(unit);
 
 #ifdef RVFI_DII
-unit zrvfi_set_instr_packet(mach_bits);
-mach_bits zrvfi_get_cmd(unit);
-mach_bits zrvfi_get_insn(unit);
+unit zrvfi_set_instr_packet(uint64_t);
+uint64_t zrvfi_get_cmd(unit);
+uint64_t zrvfi_get_insn(unit);
 bool zrvfi_step(sail_int);
 unit zrvfi_zzero_exec_packet(unit);
 unit zrvfi_halt_exec_packet(unit);
@@ -43,33 +37,20 @@ unit zprint_rvfi_exec(unit);
 unit zprint_instr_packet(uint64_t);
 #endif
 
-extern mach_bits zxlen_val;
+extern uint64_t zxlen_val;
 extern bool zhtif_done;
-extern mach_bits zhtif_exit_code;
+extern uint64_t zhtif_exit_code;
 extern bool have_exception;
 
 /* machine state */
 
-extern uint32_t zcur_privilege;
-
-extern mach_bits zPC;
-
-extern mach_bits zx1, zx2, zx3, zx4, zx5, zx6, zx7, zx8, zx9, zx10, zx11, zx12,
-    zx13, zx14, zx15, zx16, zx17, zx18, zx19, zx20, zx21, zx22, zx23, zx24,
-    zx25, zx26, zx27, zx28, zx29, zx30, zx31;
-
-extern mach_bits zmstatus;
-extern mach_bits zmepc, zmtval;
-extern mach_bits zsepc, zstval;
-
-extern mach_bits zfloat_result, zfloat_fflags;
+unit zforce_pc(uint64_t pc);
 
-struct zMcause {
-  mach_bits zMcause_chunk_0;
-};
-extern struct zMcause zmcause, zscause;
+extern uint64_t zfloat_result, zfloat_fflags;
 
-extern mach_bits zminstret;
+// Initialise types based on config values.
+void sail_set_abstract_xlen(void);
+void sail_set_abstract_ext_d_supported(void);
 
 #ifdef __cplusplus
 } // extern "C"

c_emulator/riscv_sim.cpp

@@ -449,7 +449,7 @@ void init_sail_reset_vector(uint64_t entry)
   }
 
   /* boot at reset vector */
-  zPC = rom_base;
+  zforce_pc(rom_base);
 }
 
 void init_sail(uint64_t elf_entry)
@@ -465,15 +465,18 @@ void init_sail(uint64_t elf_entry)
     rv_clint_size = UINT64_C(0);
     rv_htif_tohost = UINT64_C(0);
     */
-    zPC = elf_entry;
-  } else
+    zforce_pc(elf_entry);
+  } else {
     init_sail_reset_vector(elf_entry);
+  }
 }
 
 /* reinitialize to clear state and memory, typically across tests runs */
 void reinit_sail(uint64_t elf_entry)
 {
   model_fini();
+  sail_set_abstract_xlen();
+  sail_set_abstract_ext_d_supported();
   model_init();
   init_sail(elf_entry);
 }
@@ -676,6 +679,8 @@ int main(int argc, char **argv)
 {
   int files_start = process_args(argc, argv);
 
+  sail_set_abstract_xlen();
+  sail_set_abstract_ext_d_supported();
   model_init();
 
   if (do_report_arch) {

config/default.json

@@ -1,5 +1,6 @@
 {
   "base": {
+    "xlen": 64,
     "writable_misa": true,
     "writable_fiom": true,
     "writable_hpm_counters": {
@@ -49,7 +50,10 @@
     "A": {
       "supported": true
     },
-    "FD": {
+    "F": {
+      "supported": true
+    },
+    "D": {
       "supported": true
     },
     "V": {