Add Zilsd/Zclsd Support

Author: trdthg

model/CMakeLists.txt

@@ -78,6 +78,8 @@ foreach (xlen IN ITEMS 32 64)
                 ${vext_srcs}
                 "riscv_insts_zicbom.sail"
                 "riscv_insts_zicboz.sail"
+                "riscv_insts_zilsd.sail"
+                "riscv_insts_zclsd.sail"
             )
 
             if (variant STREQUAL "rmem")

model/riscv_extensions.sail

@@ -71,6 +71,10 @@ enum clause extension = Ext_Zcb
 enum clause extension = Ext_Zcd
 // Code Size Reduction: compressed single precision floating point loads and stores
 enum clause extension = Ext_Zcf
+// Load/Store Pair for RV32
+enum clause extension = Ext_Zilsd
+// Compressed Load/Store pair instructions
+enum clause extension = Ext_Zclsd
 
 // Bit Manipulation: Address generation
 enum clause extension = Ext_Zba

model/riscv_insts_zcf.sail

@@ -15,7 +15,7 @@
 
 /* ****************************************************************** */
 
-function clause extensionEnabled(Ext_Zcf) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_F) & xlen == 32
+function clause extensionEnabled(Ext_Zcf) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_F) & not(extensionEnabled(Ext_Zclsd)) & xlen == 32
 
 union clause ast = C_FLWSP : (bits(6), regidx)
 

model/riscv_insts_zclsd.sail

@@ -0,0 +1,73 @@
+/*=======================================================================================*/
+/*  This Sail RISC-V architecture model, comprising all files and                        */
+/*  directories except where otherwise noted is subject the BSD                          */
+/*  two-clause license in the LICENSE file.                                              */
+/*                                                                                       */
+/*  SPDX-License-Identifier: BSD-2-Clause                                                */
+/*=======================================================================================*/
+
+function clause extensionEnabled(Ext_Zclsd) = true & extensionEnabled(Ext_Zilsd) & extensionEnabled(Ext_Zca) & not(extensionEnabled(Ext_Zcf)) & xlen == 32
+
+/* ****************************************************************** */
+union clause ast = C_LDSP_RV32 : (bits(9), regidx)
+
+mapping clause encdec_compressed = C_LDSP_RV32(ui86 @ ui5 @ ui43 @ 0b000, rd) if extensionEnabled(Ext_Zclsd)
+  <-> 0b011 @ ui5 : bits(1) @ rd @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10     if extensionEnabled(Ext_Zclsd)
+
+function clause execute (C_LDSP_RV32(imm, rd)) = {
+  execute(LOAD_RV32(zero_extend(imm), sp, rd))
+}
+
+mapping clause assembly = C_LDSP_RV32(uimm, rd)
+      if xlen == 32
+  <-> "c.ldsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_9(uimm)
+      if xlen == 32
+
+/* ****************************************************************** */
+union clause ast = C_SDSP_RV32 : (bits(9), regidx)
+
+mapping clause encdec_compressed = C_SDSP_RV32(ui86 @ ui53 @ 0b000, rs2) if extensionEnabled(Ext_Zclsd)
+  <-> 0b111 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 @ 0b10               if extensionEnabled(Ext_Zclsd)
+
+function clause execute (C_SDSP_RV32(uimm, rs2)) = {
+  execute(STORE_RV32(zero_extend(uimm), rs2, sp))
+}
+
+mapping clause assembly = C_SDSP_RV32(uimm, rs2)
+      if xlen == 32
+  <-> "c.sdsp" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_9(uimm)
+      if xlen == 32
+
+/* ****************************************************************** */
+union clause ast = C_LD_RV32 : (bits(8), cregidx, cregidx)
+
+mapping clause encdec_compressed = C_LD_RV32(ui76 @ ui53 @ 0b000, rs1, rd) if extensionEnabled(Ext_Zclsd)
+  <-> 0b011 @ ui53 : bits(3) @ rs1 @ ui76 : bits(2) @ rd @ 0b00            if extensionEnabled(Ext_Zclsd)
+
+function clause execute (C_LD_RV32(uimm, rsc, rdc)) = {
+  let rd = creg2reg_idx(rdc);
+  let rs = creg2reg_idx(rsc);
+  execute(LOAD_RV32(zero_extend(uimm), rs, rd))
+}
+
+mapping clause assembly = C_LD_RV32(uimm, rsc, rdc)
+      if xlen == 32
+  <-> "c.ld" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_8(uimm)
+      if xlen == 32
+
+/* ****************************************************************** */
+union clause ast = C_SD_RV32 : (bits(8), cregidx, cregidx)
+
+mapping clause encdec_compressed = C_SD_RV32(ui76 @ ui53 @ 0b000, rs1, rs2) if extensionEnabled(Ext_Zclsd)
+  <-> 0b111 @ ui53 : bits(3) @ rs1 @ ui76 : bits(2) @ rs2 @ 0b00            if extensionEnabled(Ext_Zclsd)
+
+function clause execute (C_SD_RV32(uimm, rsc1, rsc2)) = {
+  let rs1 = creg2reg_idx(rsc1);
+  let rs2 = creg2reg_idx(rsc2);
+  execute(STORE_RV32(zero_extend(uimm), rs2, rs1))
+}
+
+mapping clause assembly = C_SD_RV32(uimm, rsc1, rsc2)
+      if xlen == 32
+  <-> "c.sd" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_8(uimm)
+      if xlen == 32

model/riscv_insts_zilsd.sail

@@ -0,0 +1,39 @@
+/*=======================================================================================*/
+/*  This Sail RISC-V architecture model, comprising all files and                        */
+/*  directories except where otherwise noted is subject the BSD                          */
+/*  two-clause license in the LICENSE file.                                              */
+/*                                                                                       */
+/*  SPDX-License-Identifier: BSD-2-Clause                                                */
+/*=======================================================================================*/
+
+function clause extensionEnabled(Ext_Zilsd) = true & xlen == 32
+
+/* ****************************************************************** */
+union clause ast = LOAD_RV32 : (bits(12), regidx, regidx)
+
+mapping clause encdec = LOAD_RV32(imm, rs1, rd) if extensionEnabled(Ext_Zilsd)
+  <-> imm @ rs1 @ 0b011 @ rd @ 0b0000011        if extensionEnabled(Ext_Zilsd)
+
+function clause execute LOAD_RV32(imm, rs1, rd) = {
+  // Use of misaligned (odd-numbered) registers is reserved.
+  assert(regidx_to_regno(rd) % 2 == 0);
+  execute(LOAD(imm, rs1, rd, false, WORD, false, false))
+  execute(LOAD(imm+4, rs1, rd+1, false, WORD, false, false))
+}
+
+mapping clause assembly = LOAD_RV32(imm, rs1, rd) <-> "ld" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_signed_12(imm) ^ "(" ^ reg_name(rs1) ^ ")"
+
+/* ****************************************************************** */
+union clause ast = STORE_RV32 : (bits(12), regidx, regidx)
+
+mapping clause encdec = STORE_RV32(imm7 @ imm5, rs2, rs1)             if extensionEnabled(Ext_Zilsd)
+  <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b011 @ imm5 : bits(5) @ 0b0100011 if extensionEnabled(Ext_Zilsd)
+
+function clause execute STORE_RV32(imm, rs2, rs1) = {
+  // Use of misaligned (odd-numbered) registers is reserved.
+  assert(regidx_to_regno(rs2) % 2 == 0);
+  execute(STORE(imm, rs2, rs1, WORD, false, false))
+  execute(STORE(imm+4, rs2+1, rs1, WORD, false, false))
+}
+
+mapping clause assembly = STORE_RV32(offset, rs2, rs1) <-> "sd" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_signed_12(offset) ^ "(" ^ reg_name(rs1) ^ ")"