Hi
I am currently writing the test for little and big endianess in the virtual memory verification.
I was trying to write the mstatush.SBE to enable big endianess for loads/stores but I am unable to do so.

mem[X,0x80000A98] -> 0xA073
mem[X,0x80000A9A] -> 0x3102
[643] [M]: 0x80000A98 (0x3102A073) csrrs zero, 0x310, t0
CSR 0x310 -> 0x00000000
CSR 0x310 <- 0x00000000 (input: 0x00000010)

I went through the sail code to figure out what is wrong and I saw the following comment here:

  /* We don't currently support changing MBE and SBE. */
  if xlen == 64 then {
    Mk_Mstatus([m.bits with 37 .. 36 = 0b00])
  } else m
}

Is there any plan to add the support for this or am I missing something?