SIMD-0272: SBPF Encoding Efficiency #272
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| simd: '0272' | ||||||
| title: SBPF Encoding Efficiency | ||||||
| authors: | ||||||
| - Alexander Meißner | ||||||
| - Lucas Steuernagel | ||||||
| category: Standard | ||||||
| type: Core | ||||||
| status: Idea | ||||||
| created: 2025-04-01 | ||||||
| feature: TBD | ||||||
| extends: SIMD-0161 | ||||||
| --- | ||||||
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| ## Summary | ||||||
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| Improve encoding efficiency in SBPF-v5. | ||||||
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| ## Motivation | ||||||
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| SBPF inherited the 64 bit intruction layout from BPF including its space | ||||||
| inefficiency. For example the 16 bit displacement is only used for memory | ||||||
| access and conditional branch instructions and the 32 bit immediate value is | ||||||
| only used in instructions with an immediate operand. Yet, all other | ||||||
| instructions still need to encode them. | ||||||
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| Additionally, there are only 10 general purpose registers which leads to a lot | ||||||
| of stack spilling and thus additional instructions and larger executable files. | ||||||
| Unlike typical CISC instruction sets like x86, which do have memory indirect | ||||||
| operands to compensate for their low number of general purpose registers, BPF | ||||||
| and thus in turn SBPF has no such thing. | ||||||
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| Reducing the instruction frame size from 64 bit to 32 bit and increasing the | ||||||
| addressable registers from 11 to 32 should dramatically improve the encoding | ||||||
| efficiency and allow for bigger (meaning more complex) on-chain programs and | ||||||
| lower rent excemption funds being required for programs at the same complexity. | ||||||
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| ## New Terminology | ||||||
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| None. | ||||||
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| ## Detailed Design | ||||||
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| ### Register Layouts | ||||||
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| The current register layout from SBPF-v1 is: | ||||||
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| | name | kind | Solana ABI | ||||||
| |-------------:|:----------------|:---------- | ||||||
| | `r0` | GPR | Return value | ||||||
| | `r1` to `r5` | GPR | Argument registers | ||||||
| | `r6` to `r9` | GPR | Call-preserved | ||||||
| | `r10` | Frame pointer | System register | ||||||
| | `pc` | Program counter | Hidden register | ||||||
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| The register layout from SBPF-v5 on is: | ||||||
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| | name | kind | Solana ABI | ||||||
| |---------------:|:----------------|:---------- | ||||||
| | `r0` | GPR | Return value | ||||||
| | `r1` to `r5` | GPR | Argument registers | ||||||
| | `r6` to `r17` | GPR | Callee-saved | ||||||
| | `r18` to `r30` | GPR | Caller-saved | ||||||
| | `r31` | Frame pointer | System register | ||||||
| | `pc` | Program counter | Hidden register | ||||||
|
There was a problem hiding this comment. We may want to burn one register and have it point to a "small data section" (.sdata) to improve the encoding efficiency of 64-bit loads. |
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| ### Instruction Layouts | ||||||
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| The current instruction layout from SBPF-v1 is: | ||||||
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| | bit index | meaning | ||||||
| | --------- | ------- | ||||||
| | 0..=2 | instruction class | ||||||
| | 3..=7 | operation code | ||||||
| | 8..=11 | destination register and first source register | ||||||
| | 12..=15 | second source register | ||||||
| | 16..=31 | offset | ||||||
| | 32..=63 | immediate | ||||||
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| The instruction layout from SBPF-v5 on depends on the instruction class, | ||||||
| see below: | ||||||
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| #### Two Source Register Operands | ||||||
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| For the 32 and 64 bit immediate-less variants of the following instructions: | ||||||
| add, sub, xor, or, and, lsh, rsh, arsh, udiv, urem, sdiv, srem, lmul, uhmul, shmul | ||||||
|
There was a problem hiding this comment. I suggest arbitrarily renaming some of the mnemonics while we have the chance.
Suggested change
Changing mnemonics would also discourage developers from writing dangerously fast programs in assembler. |
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| | bit index | meaning | ||||||
| | --------- | ------- | ||||||
| | 0..=6 | instruction class | ||||||
| | 7..=11 | destination register | ||||||
| | 12..=14 | lower 7 bits of operation code | ||||||
| | 15..=19 | first source register | ||||||
| | 20..=24 | second source register | ||||||
| | 25..=31 | upper 7 bits of operation code | ||||||
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| #### One Source Register and a 12 bit Immidiate Operand | ||||||
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| For the 32 and 64 bit immediate-valued variants of the following instructions: | ||||||
| add, sub, xor, or, and, lsh, rsh, arsh, udiv, urem, sdiv, srem, lmul, uhmul, shmul | ||||||
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| And for the following instructions: | ||||||
| ldxb, ldxh, ldxw, ldxdw, callx, mov | ||||||
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| | bit index | meaning | ||||||
| | --------- | ------- | ||||||
| | 0..=6 | instruction class | ||||||
| | 7..=11 | destination register | ||||||
| | 12..=14 | operation code | ||||||
| | 15..=19 | first source register | ||||||
| | 20..=31 | 12 bit immediate | ||||||
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| #### Two Source Register Operands and 12 bit Immidiate Operand | ||||||
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| For the immediate-less variants of the following instructions: | ||||||
| jeq, jgt, jge, jset, jne, jsgt, jsge, jlt, jle, jslt, jsle | ||||||
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| And for the following instructions: | ||||||
| stxb, stxh, stxw, stxdw | ||||||
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| | bit index | meaning | ||||||
| | --------- | ------- | ||||||
| | 0..=6 | instruction class | ||||||
| | 7..=11 | lower 5 bits of 12 bit immediate | ||||||
| | 12..=14 | operation code | ||||||
| | 15..=19 | first source register | ||||||
| | 20..=24 | second source register | ||||||
| | 25..=31 | upper 7 bits of 12 bit immediate | ||||||
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| #### 20 bit Immidiate Operand | ||||||
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| For the immediate-valued variants of the following instructions: | ||||||
| jeq, jgt, jge, jset, jne, jsgt, jsge, jlt, jle, jslt, jsle | ||||||
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| And for the following instructions: | ||||||
| stb, sth, stw, stdw, hor, call, syscall, exit, ja | ||||||
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| | bit index | meaning | ||||||
| | --------- | ------- | ||||||
| | 0..=6 | instruction class | ||||||
| | 7..=11 | destination register | ||||||
| | 12..=31 | 20 bit immediate | ||||||
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| ## Alternatives Considered | ||||||
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| None. | ||||||
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| ## Impact | ||||||
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| Like the other SBPF versions these changes will be hidden inside the compiler | ||||||
| toolchain and be transparent to the dApp developers. | ||||||
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| ## Security Considerations | ||||||
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| None. | ||||||
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| ## Drawbacks | ||||||
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| This increases the complexity of the instruction decoder and thus slows down | ||||||
| interpreter based execution. Whether the increased encoding efficiency, reduced | ||||||
| memory bandwidth and cache pressure can make up for it depends on the | ||||||
| implementation. | ||||||
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I've seen many function calls use more than five registers to store arguments, so allocating more registers here (six or seven) would be beneficial to avoid stack spills.