v1.11.5

What's Changed

• Rework caches; use "write-through" strategy by @stnolting in #1259
• Rework locking of processor-internal bus by @stnolting in #1260
• minor edits and optimizations by @stnolting in #1262
• ✨ add cache burst transfers by @stnolting in #1263
• [bus] add explicit burst signal to internal processor bus by @stnolting in #1265
• 🐛 Fix missing burst signal in bus register stage by @stnolting in #1266
• ⚠️ make MCAUSE CSR read-only by @stnolting in #1267
• ⚠️ [inter-processor communication] remove hardware spinlocks and inter-core communication links by @stnolting in #1268
• 🐛 fix CPU bus issues by @stnolting in #1270

Full Changelog: v1.11.4...v1.11.5