v1.11.8

New Features

• add double-trap exception (loosely based on the RISC-V Smdbltrp ISA extension)
• add support for hardware-assisted watchpoints (on-chip debugger)
• add configurable number of hardware break-/watchpoint (0..16)

What's Changed

• remove WDT "strict" bit; minor code edits and cleanups by @stnolting in #1293
• 🧪 add double-trap exception by @stnolting in #1294
• Rework RTE trap handler look-up-table by @stnolting in #1295
• [rte] cleanups and optimizations by @stnolting in #1299
• minor rtl edits and cleanups by @stnolting in #1302
• Feature: Libero support by @hughbreslin in #1300
• [ocd] add support for hardware watchpoints by @stnolting in #1303
• ✨ add configurable number of break-/watchpoints by @stnolting in #1304
• minor rtl edits and cleanups by @stnolting in #1307
• ⚠️ [top] remove HART_BASE generic by @stnolting in #1308
• [cache] fix minimal cache block size by @stnolting in #1310

New Contributors

• @hughbreslin made their first contribution in #1300

Full Changelog: v1.11.7...v1.11.8

v1.11.7

What's Changed

• [cpu] Minor rtl optimizations and cleanups by @stnolting in #1283
• upgrade TRNG to neoTRNG v3.3 by @stnolting in #1284
• ✨ on chip debugger: add semihosting support by @stnolting in #1285
• ⚠️ combine SLINK's RX and TX interrupts into a single interrupt by @stnolting in #1286
• ✨ add TRNG interrupt by @stnolting in #1287
• ⚠️ rework UART "TX FIFO full" status flag by @stnolting in #1288
• ⚠️ combine UART's RX and TX interrupts into a single interrupt by @stnolting in #1289
• Minor rtl edits and optimizations by @stnolting in #1291
• Remove enable logic for SoC-wide clock generator by @stnolting in #1292

Full Changelog: v1.11.6...v1.11.7

v1.11.6

What's Changed

• 🐛 fix byte-enable bus signal for instruction fetch accesses by @stnolting in #1272
• minor rtl edits and cleanups by @stnolting in #1273
• ⚠️ CFS IO rework by @stnolting in #1274
• ⚠️ remove CRC module by @stnolting in #1275
• Rework IMEM & DMEM RAM style by @stnolting in #1277
• [cpu] rework instruction trap logic by @stnolting in #1278
• 🧪 rework DMA controller by @stnolting in #1279
• ⚠️ Rename IMEM/DMEM configuration generics by @stnolting in #1280
• Add optional IMEM/DMEM output register stages by @stnolting in #1281

Full Changelog: v1.11.5...v1.11.6

v1.11.5

What's Changed

• Rework caches; use "write-through" strategy by @stnolting in #1259
• Rework locking of processor-internal bus by @stnolting in #1260
• minor edits and optimizations by @stnolting in #1262
• ✨ add cache burst transfers by @stnolting in #1263
• [bus] add explicit burst signal to internal processor bus by @stnolting in #1265
• 🐛 Fix missing burst signal in bus register stage by @stnolting in #1266
• ⚠️ make MCAUSE CSR read-only by @stnolting in #1267
• ⚠️ [inter-processor communication] remove hardware spinlocks and inter-core communication links by @stnolting in #1268
• 🐛 fix CPU bus issues by @stnolting in #1270

Full Changelog: v1.11.4...v1.11.5

v1.11.4

What's Changed

• Make hardware breakpoint optional; constrain to debug-mode only by @stnolting in #1239
• 🐛 [bootloader] fix privilege at application start by @stnolting in #1241
• Optimize round-robin bus switch: remove idle cycles by @stnolting in #1244
• Add bus lock feature by @stnolting in #1245
• Optimize cache system by @stnolting in #1248
• Rework newlib system calls by @stnolting in #1249
• ⚠️ Rework processor-internal bus protocol by @stnolting in #1252
• Add full-scale AXI4 bridge by @stnolting in #1253
• [docs] fix dead link to setups by @josuah in #1255
• ⚠️ Remove external bus interface cache (xbus-cache) by @stnolting in #1256
• ⚠️ Rework cache configuration options by @stnolting in #1257

New Contributors

• @josuah made their first contribution in #1255

Full Changelog: v1.11.3...v1.11.4

v1.11.3

What's Changed

• [docs] inline Wavedrom scripts by @stnolting in #1208
• docs: datasheet: cpu: fix name for the "A" ISA extension by @henrikbrixandersen in #1209
• build: rebuild exe when header files change by @ecstrema in #1212
• fix litex boot by @pepijndevos in #1211
• ⚠️ Remove CPU clock gating option by @stnolting in #1214
• [rtl/sw] Add twd dummy byte, add twd bootloader and smaller fixes by @LukasP46 in #1210
• ✨ Add 32 hardware spinlocks by @stnolting in #1220
• 🐛 fix PWM prescaler by @stnolting in #1222
• 🐛 [linker] fix alignment of init/fini arrays by @stnolting in #1224
• Minor rtl edits and optimizations by @stnolting in #1225
• [sw/lib] add restart/reset functions by @stnolting in #1226
• 🐛 [SDI] fix input synchronizer by @stnolting in #1227
• [sw/lib/neoled] fix neoled "irq_mode" not a applied in "neorv32_neoled_setup" and [sw/lib/neoled] updated doxygen comments by @SirBramble in #1228
• Add support for setting PWM polarity by @henrikbrixandersen in #1230
• [sw] cleanup main software makefile, add git tag, add verbosity configuration by @stnolting in #1231
• [sw/bootloader] TWI fix for bootloader by @SirBramble in #1229
• Rework bootloader by @stnolting in #1215
• [rtl/pmp] fix multiple signal assignment by @NikLeberg in #1236
• [rtl/core/twi] delay sda low by @SirBramble in #1237

New Contributors

• @SirBramble made their first contribution in #1228

Full Changelog: v1.11.2...v1.11.3

v1.11.2

What's Changed

• ✨ add support for Zalrsc ISA extension by @stnolting in #1181
• Minor rtl optimizations and cleanups by @stnolting in #1182
• Source-out CPU front-end by @stnolting in #1183
• ⚠️ Software libraries cleanup by @stnolting in #1186
• Fix Bootloader Makefile UART_BAUD by @lebruu in #1189
• 🐛 fix bug in Zalrsc ISA extension by @stnolting in #1190
• [rtl] minor edits and cleanups by @stnolting in #1191
• [cpu] relocate CPU counters by @stnolting in #1192
• minor rtl edits by @stnolting in #1193
• ⚠️ rework DMA and GPTMR by @stnolting in #1194
• rtl: processor_templates: enable Zicntr ISA extension on minimal templates by @henrikbrixandersen in #1196
• Fix: quote readlink to fix windows make check by @ecstrema in #1197
• fix: increment location counter with heap size by @brkydnc in #1201
• Add NUMA LiteX configuration by @pepijndevos in #1204
• 🐛 Fix Zbb shift instructions by @stnolting in #1206
• ⚠️ rename SPI & TWI transfer functions by @stnolting in #1207

New Contributors

• @lebruu made their first contribution in #1189
• @ecstrema made their first contribution in #1197
• @brkydnc made their first contribution in #1201
• @pepijndevos made their first contribution in #1204

Full Changelog: v1.11.1...v1.11.2

v1.11.1

What's Changed

• [rtl] reset SDA and SCL of TWI and TWD to '1' by @LukasP46 in #1167
• ⚠️ rename JEDEC ID generic; minor rtl edits and optimizations by @stnolting in #1168
• 🐛 fix BOOTROM addressing by @stnolting in #1171
• 🐛 Fix crt0's main entry address being overridden by constructors by @stnolting in #1172
• Minor rtl optimizations and cleanups by @stnolting in #1174
• ⚠️ remove execute in-place (XIP) module by @stnolting in #1175
• [cfs] Add missing CFS clock gen enable signal. by @Sazzach in #1177
• ✨ add memory coherency logic by @stnolting in #1176
• Doc ds fixes by @DAR0001 in #1178
• [docs] SPI: minor fixes by @stnolting in #1166
• Minor rtl edits and cleanups by @stnolting in #1179
• ⚠️ rename UART RTS/CTS signals by @stnolting in #1180

New Contributors

• @Sazzach made their first contribution in #1177
• @DAR0001 made their first contribution in #1178

Full Changelog: v1.11.0...v1.11.1

v1.11.0

What's Changed

• fix CSR read operations (side effects) by @stnolting in #1145
• [sw/bootloader] add TWI boot option by @LukasP46 in #1108
• SMP dual-core cleanups by @stnolting in #1146
• [control] separate fence and fence.i instructions by @stnolting in #1149
• ⚠️ [rte] use a single, global trap handler table by @stnolting in #1150
• Minor rtl edits and cleanup; 🐛 fix multiple drivers bug by @stnolting in #1151
• [sw/bootloader] aligned trap handler by @LukasP46 in #1153
• [top] add WDT and OCD reset outputs by @stnolting in #1152
• ✨ add GPIO interrupt(s) by @stnolting in #1159
• [ci] update GHDL setup by @stnolting in #1160
• Update neorv32_ProcessorTop_MinimalBoot.vhd by @ohenley in #1156
• 🐛 [twd] fix some design flaws by @stnolting in #1161
• atomic memory access updates and improvements by @stnolting in #1163
• [rtl] use past SDA in twd FSM transition by @LukasP46 in #1165

New Contributors

• @ohenley made their first contribution in #1156

Full Changelog: v1.10.9...v1.11.0

v1.10.9

What's Changed

• ⚠️ Replace MTIME by CLINT by @stnolting in #1130
• Add "out-of-band" signals to internal bus interface by @stnolting in #1131
• Update neorv32_cpu_control.vhd by @mahdi259 in #1128
• ⚠️ rename SYSINFO.MEM -> SYSINFO.MISC by @stnolting in #1134
• 🧪 add multi-hart support to on-chip-debugger's debug module by @stnolting in #1132
• [clint] automate MTIMECMP selection by @stnolting in #1136
• ⚠️ Move RTE information functions to AUX library by @stnolting in #1137
• ✨ add smp dual-core support by @stnolting in #1135
• ⚠️✨ replace Zalrsc ISA extension by Zaamo ISA extension by @stnolting in #1141
• ✨ [dual-core] add inter-core communication by @stnolting in #1142
• [ci] workaround - ghdl installation by @stnolting in #1143
• Minor rtl edits and cleanups by @stnolting in #1144

Full Changelog: v1.10.8...v1.10.9