v1.10.8

What's Changed

• 🧪 Shrink bootloader ISA and RAM requirements by @stnolting in #1118
• [sim] rework default testbench by @stnolting in #1119
• ⚠️ rework TRNG by @stnolting in #1120
• ✨ add new module: device-mode I²C controller ("TWD") by @stnolting in #1121
• Docs: removed Chapter about VHDL Development Environment by @vogma in #1122
• 🧪 [pmp] use time-multiplex approach by @stnolting in #1105
• minor rtl cleanups and optimization by @stnolting in #1123
• Relocate clock gating switch by @stnolting in #1124
• ⚠️ Rename CPU tuning options / generics by @stnolting in #1125
• ⚠️ Rework IO/peripheral address space by @stnolting in #1126

New Contributors

• @vogma made their first contribution in #1122

Full Changelog: v1.10.7...v1.10.8

v1.10.7

What's Changed

• ⚠️ Relocate VUnit testbench to another sub-repository (neorv32-vunit) by @stnolting in #1083
• [github workflow] remove packages by @stnolting in #1085
• 🧪 convert VHDL memory images into full-scale VHDL packages by @stnolting in #1084
• ⚠️ Rework processor boot configuration by @stnolting in #1086
• Minor rtl edits and cleanups by @stnolting in #1090
• Rework default testbench by @stnolting in #1093
• 🧪 Use xpack risc-v gcc as default prebuilt toolchain by @stnolting in #1091
• [CPU control] large code cleanup by @stnolting in #1099
• Fixed typo and cpu_alu architecture renaming for consistency by @LukasP46 in #1102
• [docs/makefile] Copy figures also for single targets by @LukasP46 in #1101
• [rtl] fix some Verilog [sic] issues by @stnolting in #1103
• [sw] Use build folder and add example for more complex project structure by @LukasP46 in #1107
• [TWI] add bus sensing logic by @stnolting in #1111
• [sw] Add UART disable tag by @LukasP46 in #1112
• ✨ add ONEWIRE command FIFO; 🐛 fix ONEWIRE status flag by @stnolting in #1113
• use vhdl 2008 standard in ghdl simulations by @csantosb in #1096
• [docs] Fix missing " in makefile by @LukasP46 in #1117

New Contributors

• @LukasP46 made their first contribution in #1102
• @csantosb made their first contribution in #1096

Full Changelog: v1.10.6...v1.10.7

v1.10.6

What's Changed

• ⚠️ rework CFU handshake interface by @stnolting in #1046
• ⚠️ remove A ISA extension, add Zalrsc ISA extension by @stnolting in #1047
• Uprade neoTRNG to version 3.2 by @stnolting in #1048
• ⚠️ rework PWM module by @stnolting in #1049
• [ci] remove python doit by @stnolting in #1055
• ✨🔒 add optional on-chip debugger authentication by @stnolting in #1053
• ⚠️ Remove OCD's DM legacy mode by @stnolting in #1056
• [sw/lib] restore previous registers in neorv32_xirq_get_num function to avoid side effects by @donlon in #1057
• [vivado ip] hide entire AXI-Stream interface in block diagram if disabled by @donlon in #1058
• [rtl/system_integration] create individual module for AXI4 Lite bridge by @donlon in #1063
• Update dhry_1.c by @mahdi259 in #1066
• [vivado ip] reorganize Vivado IP GUI by @donlon in #1064
• [rtl] minor RTL edits by @stnolting in #1068
• [vivado ip] make m_axi (XBUS) interface optional by @donlon in #1067
• ⚠️ Rework XIRQ - remove "pending" register by @stnolting in #1071
• 🧪 Rework makefile/linker script memory configuration by @stnolting in #1072
• [sw/common] Cleanup central makefile and linker script by @stnolting in #1077

New Contributors

• @donlon made their first contribution in #1057
• @mahdi259 made their first contribution in #1066

Full Changelog: v1.10.5...v1.10.6

v1.10.5

What's Changed

• [rtl] signal renamings and cleanups to make the code more readable by @stnolting in #1026
• 🐛 fix minor bug in FPU MUL instruction by @stnolting in #1028
• [rtl] remove redundant prog_buf by @NikLeberg in #1030
• [rtl] fix generate spelling by @NikLeberg in #1031
• [cpu] rework ALU instruction decoding and CPU co-processor interface by @stnolting in #1032
• ✨ [cpu] add support for RISC-V scalar cryptography ISA extensions by @stnolting in #1033
• Fix typo trap table by @BEforlin in #1035
• Add Zkt ISA extension by @stnolting in #1036
• ✨ add support for RISC-V Zbkb ISA extension by @stnolting in #1037
• ✨ add support for RISC-V Zbkc ISA extension by @stnolting in #1038
• Add Zkn ISA extension by @stnolting in #1039
• ✨ add support for RISC-V Zks* ISA extensions by @stnolting in #1040
• ⚠️ Rename CPU ISA configuration generics by @stnolting in #1041
• ⚠️ split B ISA extension into individual sub-extensions by @stnolting in #1044

New Contributors

• @BEforlin made their first contribution in #1035

Full Changelog: v1.10.4...v1.10.5

v1.10.4

What's Changed

• minor RTL cleanups and optimizations by @stnolting in #1004
• 🧪 Remove "loop" from memory initialization function by @stnolting in #1005
• minor fixes in OCD by @NikLeberg in #1006
• [sw] fix sysinfo doxygen header by @NikLeberg in #1007
• optimize CSR address logic by @stnolting in #1008
• Minor rtl/CSR optimizations by @stnolting in #1010
• Cleanup debug symbols by @stnolting in #1009
• minor HDL cleanups and otimizations by @stnolting in #1014
• Cleanup and extend watch dog's reset-cause logic by @stnolting in #1015
• ⚠️ Refactor RTL files / hierarchy by @stnolting in #1017
• 🐛 fix B.CTZ decoding regression bug by @stnolting in #1018
• Massive rtl code cleanup by @stnolting in #1019
• 🐛 fix stack alignment upon first procedure entry by @stnolting in #1021

Full Changelog: v1.10.3...v1.10.4

v1.10.3

What's Changed

• ⚠️ rework CFU (remove R5-type instructions) by @stnolting in #971
• Rework (and auto-generate) file-list files by @stnolting in #972
• [docs] fix spelling by @NikLeberg in #975
• [vivado_ip] fix error when AXI port is unconnected by @stnolting in #976
• [vivado_ip] fix unconnected variable-size inputs by @stnolting in #978
• [vivado_ip] constrain minimal size of variable-sized output ports by @stnolting in #980
• Minor RTL edits by @stnolting in #984
• ⚠️ reorganize core RTL files ⚠️ by @stnolting in #985
• [rtl] minor timing and area optimizations by @stnolting in #990
• RTL reworks, cleanups and optimizations by @stnolting in #996
• 🐛 fix minor regression bug; minor RTL optimizations by @stnolting in #998

Full Changelog: v1.10.2...v1.10.3

v1.10.2

What's Changed

• minor software framework cleanups and optimizations by @stnolting in #940
• minor rtl cleanups and optimizations by @stnolting in #941
• minor rtl edits by @stnolting in #948
• [image_generator] add *.mif memory initialization file format by @stnolting in #949
• Add option to disable SYSINFO module by @stnolting in #952
• 🐛 Fix SDI "TX FIFO full" flag by @stnolting in #953
• [SPI] add programmable chip-select operations by @stnolting in #954
• Minor SDI edits by @stnolting in #955
• 🐛 [newlib] fix broken sbrk function by @stnolting in #957
• [rtl] clean-up simulation-only pragmas by @stnolting in #956
• 🔒 restrict access to IO modules to privileged (machine-mode) software by @stnolting in #958
• Minor SW framework edits to fix c++ warnings by @stnolting in #964
• Make SYSINFO CLK writable by @stnolting in #966

Full Changelog: v1.10.1...v1.10.2

v1.10.1

What's Changed

• ⚠️ remove redundant JTAG reset signal (TRST) by @stnolting in #928
• minor rtl code clean-ups by @stnolting in #929
• Add UART FIFO clear flags; add DMA FIRQ interrupt configuration by @stnolting in #930
• Minor rtl edits/cleanups by @stnolting in #931
• ⚠️ rework CFU interface by @stnolting in #932
• minor software updates and fixes by @stnolting in #933
• [sw] add auxiliary/helper functions library by @stnolting in #934
• minor rtl edits and cleanups by @stnolting in #935
• Minor sw & hw cleanups by @stnolting in #936
• 🧪 Add experimental XBUS (Wishbone) to AHB3-Lite bridge by @stnolting in #937
• ⚠️ Remove AMO_RVS_GRANULARITY generic by @stnolting in #938
• ⚠️ rework GPTMR by @stnolting in #939

Full Changelog: v1.10.0...v1.10.1

v1.10.0

What's Changed

• Add NEORV32 as Vivado IP by @stnolting in #894
• Cleanup SW library by @stnolting in #900
• Add back Dhrystone port by @stnolting in #901
• Update neorv32_sdi.vhd - Minor typo correction by @ucycg in #903
• Add COE and MEM file generator options by @stnolting in #904
• [FPU] prevent GCC from emitting fused multiply-add instructions by @stnolting in #905
• Add SLINK routing information ports by @stnolting in #908
• Make XIRQ trigger configuration programmable by @stnolting in #911
• Add HDL file list files by @stnolting in #909
• Relocate f files by @stnolting in #912
• Add variable-sized ports to Vivado IP block by @stnolting in #913
• Fix uncached/cached access priority by @stnolting in #915
• [xbus] access type identifier (tag signal) by @stnolting in #917
• [sw/lib] ⚠️ rework gpio_pin_set function by @stnolting in #921
• [rtl] TRNG: add data-available interrupt by @stnolting in #922
• Minor code cleanups by @stnolting in #925
• ✨ Add pre-configured Eclipse example project by @stnolting in #926

New Contributors

• @ucycg made their first contribution in #903

Full Changelog: v1.9.9...v1.10.0

v1.9.9

What's Changed

• minor rtl clean-ups and optimization by @stnolting in #872
• use simplified VHDL file headers by @stnolting in #873
• ⚠️ rename SLINK data interface registers by @stnolting in #874
• ⚠️ simplify XBUS gateway by @stnolting in #876
• [DMA] use FIRQ select instead of FIRQ mask by @stnolting in #877
• rtl logic optimization and cleanups by @stnolting in #880
• fix external debug-halt vs. exception concurrency by @stnolting in #882
• minor rtl fixes by @stnolting in #883
• [rtl] fix single-step halting by @stnolting in #887
• minor rtl cleanups by @stnolting in #889
• Fix UART receiver by @Unike267 in #891

Full Changelog: v1.9.8...v1.9.9