v1.12.7

What's Changed

• rtl edits, cleanups and optimizations by @stnolting in #1462
• [hpm] rework HPM events by @stnolting in #1463
• ✨ add support for RISC-V Smcntrpmf ISA extension (counter privilege-mode filtering) by @stnolting in #1464
• Add description to TOPCMP in svd by @kurtjd in #1466
• minor CPU cleanups and optimizations by @stnolting in #1465
• minor rtl edits by @stnolting in #1467
• Add Rust support to user guide by @kurtjd in #1469
• 🐛 fix bus timeout issue; minor rtl edits by @stnolting in #1470
• Relax cache size configuration constraints by @stnolting in #1471
• ⚠️ Rename ALU co-processor modules by @stnolting in #1472
• Make minor UART doc fixes by @kurtjd in #1473
• Minor RTL cleanups and optimizations by @stnolting in #1474

New Contributors

• @kurtjd made their first contribution in #1466

Full Changelog: v1.12.6...v1.12.7

v1.12.6

What's Changed

• Add Verilog conversion flow by @stnolting in #1438
• Add Ada mention to READMEs by @ohenley in #1420
• fix minor OCD command-execution issue by @stnolting in #1440
• Move processor templates to neorv32-setups repository by @stnolting in #1442
• [uart] remove sim-mode logging to file by @stnolting in #1443
• minor rtl edits and cleanups by @stnolting in #1444
• [pwm] add phase-correct PWM operation mode by @stnolting in #1445
• Fix missing quote in help message (unterminated string) by @tzf230201 in #1447
• Rework CPU control unit by @stnolting in #1449
• Bump actions/download-artifact from 6 to 7 by @dependabot[bot] in #1451
• Bump actions/upload-artifact from 5 to 6 by @dependabot[bot] in #1452
• Fix SMP dual-core boot by @stnolting in #1450
• Minor cleanups by @stnolting in #1455
• [cpu] RTL cleanups by @stnolting in #1456
• Add RISC-V architecture compatibility tests by @stnolting in #1458
• [cpu] remove mxcsr CSR by @stnolting in #1459
• Rework register file: allow to select specific architecture for better technology mapping by @stnolting in #1460
• minor rtl edits and cleanups by @stnolting in #1461

New Contributors

• @tzf230201 made their first contribution in #1447

Full Changelog: v1.12.5...v1.12.6

v1.12.5

What's Changed

• [rtl] minor code edits by @stnolting in #1422
• ⚠️ rework PWM module by @stnolting in #1424
• [tracer] fix simulation log operand decoding by @stnolting in #1425
• 🧪 [rte] cleanup and rework by @stnolting in #1427
• ⚠️ Rework general purpose timer (GPTMR) by @stnolting in #1428
• [pwm] extend max number of PWM channels from 16 to 32 by @stnolting in #1429
• [ci] update xpack riscv gcc by @stnolting in #1430
• ✨ [cpu] add support for RISC-V Zimop ISA extension by @stnolting in #1431
• Bump actions/checkout from 5 to 6 by @dependabot[bot] in #1432
• 🐛 fix PMP bugs by @stnolting in #1433
• [semihosting] add option to redirect UART data by @stnolting in #1434
• [OCD] optimize CPU-DM communication by @stnolting in #1435

Full Changelog: v1.12.4...v1.12.5

v1.12.4

What's Changed

• [rtl] rework DM by @stnolting in #1396
• 🐛 [rtl] fix CLZ and CTZ instructions by @stnolting in #1397
• [docs] xbus: fix/clarify CTI values by @stnolting in #1399
• [sdext] fix trigger type identification by @stnolting in #1400
• ⚠️ [CFU] remove r4-type instruction support by @stnolting in #1402
• [bus] clean-up processor-internal bus; refine reservation-set controller by @stnolting in #1407
• [sw/example] mark output as early-clobber in unaligned-load test by @vogma in #1406
• [pmp] improve timing by @stnolting in #1408
• counter optimizations and PMP logic cleanup by @stnolting in #1410
• 🐛 [clint] fix register read-back by @stnolting in #1411
• [docs] use Doxygen only for documenting the API by @stnolting in #1413
• Bump actions/download-artifact from 5 to 6 by @dependabot[bot] in #1414
• Bump actions/upload-artifact from 4 to 5 by @dependabot[bot] in #1415
• ✨ [cpu] add experimental support for RISC-V Zibi ISA extension by @stnolting in #1418

Full Changelog: v1.12.3...v1.12.4

nightly release

This release includes up-to-date PDF builds of the documentation.

• data sheet: NEORV32-nightly.pdf
• user guide: NEORV32_UserGuide-nightly.pdf

v1.12.3

What's Changed

• [XBUS] re-add timeout configuration generic by @stnolting in #1383
• Rework execution trace interface by @stnolting in #1384
• 🧪 extend trace port to support "RISC-V formal interface" (RVFI) by @stnolting in #1385
• Rework NEORV32 executable image generator by @stnolting in #1388
• [rtl] minor code cleanups and optimizations by @stnolting in #1389
• rework JTAG interface by @stnolting in #1390
• [rtl] add multiplier primitive by @stnolting in #1391
• 🐛 [rtl] FPU cleanups and minor bug fix by @stnolting in #1392
• 🐛 [dtm] fix bypass register; further code optimizations by @stnolting in #1393
• [system_integration] move libero setup to neorv32-setups repository by @stnolting in #1394
• minor rtl edits and cleanups by @stnolting in #1395

Full Changelog: v1.12.2...v1.12.3

v1.12.2

What's Changed

• Rework bootloader; add optional SD card boot option by @stnolting in #1361
• 🐛 [dm] fix command.transfer flag logic by @stnolting in #1363
• minor rtl edits by @stnolting in #1364
• [tracer] update simulation-mode instruction decoding by @stnolting in #1366
• [tracer] update simulation-mode trace logging by @stnolting in #1368
• Bump actions/download-artifact from 4 to 5 by @dependabot[bot] in #1372
• Bump mattnotmitt/doxygen-action from 1.2.1 to 1.12.0 by @dependabot[bot] in #1371
• Bump actions/checkout from 4 to 5 by @dependabot[bot] in #1370
• minor edits and cleanups by @stnolting in #1375
• 🐛 fix unaligned instruction fetch bus error; do not trigger co-processors if instruction exception by @stnolting in #1376
• ⚠️ remove CFU CSRs by @stnolting in #1377
• Correct typo neorv323_package -> neorv32_package by @alyxazon in #1379
• [cpu] minor logic optimizations by @stnolting in #1381

New Contributors

• @dependabot[bot] made their first contribution in #1372
• @alyxazon made their first contribution in #1379

Full Changelog: v1.12.1...v1.12.2

v1.12.1

What's Changed

• [rtl] derive all memories from generic RAM primitives by @stnolting in #1347
• [rtl] add all-new FIFO primitive by @stnolting in #1349
• [demo_semihosting] use 4-byte instead of 16-byte alignment by @vogma in #1350
• 🐛 fix simulation memory-component by @stnolting in #1352
• ⚠️ simplify SLINK, SPI and NEOLED modules by @stnolting in #1353
• ⚠️ simplify UART and SDI modules by @stnolting in #1354
• simplify ROM images (VHDL packages for IMEM/BOOTROM) by @stnolting in #1355
• [rtl] minor code-cleanups and optimizations by @stnolting in #1357
• [sdi] add RX & TX FIFO clear flags by @stnolting in #1358
• ⚠️ rework TWD module by @stnolting in #1359
• fix minor RISC-V incompatibilities by @stnolting in #1360

Full Changelog: v1.12.0...v1.12.1

v1.12.0

What's Changed

• ⚠️ [CPU] remove double-trap exception by @stnolting in #1332
• minor fixes and optimizations by @stnolting in #1333
• Add NEORV32-specifc "machine control and status" CSR (mxcsr) by @stnolting in #1335
• Add new tuning option: Constant-time branches by @stnolting in #1338
• Rework bus access error logic by @stnolting in #1339
• ⚠️ [SYSINFO] rework layout of "MISC" information register by @stnolting in #1342
• [rtl] replace individual IMEM & DMEM modules by a generic memory component by @stnolting in #1344
• [Vivado IP] Remove relative paths from the IP-packaging script by @stnolting in #1341
• rtl code cleanups and optimizations by @stnolting in #1345
• 🐛 [dma] fix byte-enable signal for byte-reads by @stnolting in #1346

Full Changelog: v1.11.9...v1.12.0

v1.11.9

What's Changed

• 🐛 fix double-trap tracking bug by @stnolting in #1312
• ✨ add new module: execution trace buffer (TRACER) by @stnolting in #1313
• Cleanup UART simulation logging by @stnolting in #1314
• Replace trace with trace_s in the top by @Unike267 in #1316
• Add GDB tracer support by @stnolting in #1317
• [tracer] write full trace log to file by @stnolting in #1318
• ✨ add support for RISC-V Zcb ISA extension by @stnolting in #1320
• extend tracer simulation log; improve semihosting by @stnolting in #1322
• Make cache/AXI bursts optional by @stnolting in #1324
• Minor rtl edits and cleanups by @stnolting in #1325
• minor rtl edits and cleanups by @stnolting in #1331

Full Changelog: v1.11.8...v1.11.9