This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
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Oct 19, 2023 - SystemVerilog
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async-fifo
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UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.
makefile verification vcs systemverilog fifo cdc uvm testbench sva metastability functional-coverage async-fifo questa-sim
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Aug 22, 2025 - SystemVerilog
ITCH parser v3 - Async FIFO with gray code CDC. 100% reliability. Code reduction: 677→395 lines (41% simpler).
fpga vhdl xilinx low-latency protocol-parser production-ready cdc trading-systems gray-code nasdaq-itch artix-7 async-fifo
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Jan 24, 2026 - VHDL
CDC-safe asynchronous FIFO in SystemVerilog with Gray pointers, 2FF synchronizers, SVA, and reproducible simulation/synthesis flows.
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Feb 23, 2026 - Verilog
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