Type refactor within MetaModel

[jokap11]

Refactored the typing system to establish a single, consistent, and centralized type model.

Summary:
Typing has been moved out of the arch file and completely redesigned,

• with TypeKind as the core abstraction instead of signed boolean
• Literals have been consolidated into a unified Literal type.
• Type inference and the ty/size API are now consistent.
• Attributes have been separated into their own class.
• Scalars are abstracted into Symbols with a type
  This lays hopefully the foundation for future extensions such as arrays, structs, and unions.

[jokap11]

@PhilippvK I think this is so far rdy for merging/further extensions (see https://github.com/tum-ei-eda/M2-ISA-R/tree/behav_array_support)

[jokap11]

How can I test this @PhilippvK

hans@jktpu:~/m2isar/arch_type/xmnn-isax-flow$ diff -r   -I '^ \* Generated on .*'   cdsl/gen_output/top/RV32IMACFD   cdsl/compare/top/RV32IMACFD/
diff -r -I '^ \* Generated on .*' cdsl/gen_output/top/RV32IMACFD/CMakeLists.txt cdsl/compare/top/RV32IMACFD/CMakeLists.txt
1c1
< # Generated on Wed, 17 Jun 2026 16:37:37 +0200.
---
> # Generated on Wed, 17 Jun 2026 16:36:51 +0200.
diff -r -I '^ \* Generated on .*' cdsl/gen_output/top/RV32IMACFD/RV32IMACFDArch.cpp cdsl/compare/top/RV32IMACFD/RV32IMACFDArch.cpp
74a75,79
>     for (int i = 0; i < 32; ++i)
>     {
>         rv32imacfdcpu->ins_X[i] = 0;
>         rv32imacfdcpu->X[i] = &rv32imacfdcpu->ins_X[i];
>     }
80c85,118
<     for (int i = 0; i < 32; ++i)
---
> 
>     rv32imacfdcpu->ZERO = 0;
>     rv32imacfdcpu->RA = 0;
>     rv32imacfdcpu->SP = 0;
>     rv32imacfdcpu->GP = 0;
>     rv32imacfdcpu->TP = 0;
>     rv32imacfdcpu->T0 = 0;
>     rv32imacfdcpu->T1 = 0;
>     rv32imacfdcpu->T2 = 0;
>     rv32imacfdcpu->S0 = 0;
>     rv32imacfdcpu->S1 = 0;
>     rv32imacfdcpu->A0 = 0;
>     rv32imacfdcpu->A1 = 0;
>     rv32imacfdcpu->A2 = 0;
>     rv32imacfdcpu->A3 = 0;
>     rv32imacfdcpu->A4 = 0;
>     rv32imacfdcpu->A5 = 0;
>     rv32imacfdcpu->A6 = 0;
>     rv32imacfdcpu->A7 = 0;
>     rv32imacfdcpu->S2 = 0;
>     rv32imacfdcpu->S3 = 0;
>     rv32imacfdcpu->S4 = 0;
>     rv32imacfdcpu->S5 = 0;
>     rv32imacfdcpu->S6 = 0;
>     rv32imacfdcpu->S7 = 0;
>     rv32imacfdcpu->S8 = 0;
>     rv32imacfdcpu->S9 = 0;
>     rv32imacfdcpu->S10 = 0;
>     rv32imacfdcpu->S11 = 0;
>     rv32imacfdcpu->T3 = 0;
>     rv32imacfdcpu->T4 = 0;
>     rv32imacfdcpu->T5 = 0;
>     rv32imacfdcpu->T6 = 0;
>     for (int i = 0; i < 8; ++i)
82,83c120,124
<         rv32imacfdcpu->ins_X[i] = 0;
<         rv32imacfdcpu->X[i] = &rv32imacfdcpu->ins_X[i];
---
>         rv32imacfdcpu->FENCE[i] = 0;
>     }
>     for (int i = 0; i < 8; ++i)
>     {
>         rv32imacfdcpu->RES[i] = 0;
85d125
< 
87a128,130
>     rv32imacfdcpu->MSTATUS = 0;
>     rv32imacfdcpu->MIE = 0;
>     rv32imacfdcpu->MIP = 0;
89a133,167
>     rv32imacfdcpu->X[0] = &rv32imacfdcpu->ZERO;
>     rv32imacfdcpu->X[1] = &rv32imacfdcpu->RA;
>     rv32imacfdcpu->X[2] = &rv32imacfdcpu->SP;
>     rv32imacfdcpu->X[3] = &rv32imacfdcpu->GP;
>     rv32imacfdcpu->X[4] = &rv32imacfdcpu->TP;
>     rv32imacfdcpu->X[5] = &rv32imacfdcpu->T0;
>     rv32imacfdcpu->X[6] = &rv32imacfdcpu->T1;
>     rv32imacfdcpu->X[7] = &rv32imacfdcpu->T2;
>     rv32imacfdcpu->X[8] = &rv32imacfdcpu->S0;
>     rv32imacfdcpu->X[9] = &rv32imacfdcpu->S1;
>     rv32imacfdcpu->X[10] = &rv32imacfdcpu->A0;
>     rv32imacfdcpu->X[11] = &rv32imacfdcpu->A1;
>     rv32imacfdcpu->X[12] = &rv32imacfdcpu->A2;
>     rv32imacfdcpu->X[13] = &rv32imacfdcpu->A3;
>     rv32imacfdcpu->X[14] = &rv32imacfdcpu->A4;
>     rv32imacfdcpu->X[15] = &rv32imacfdcpu->A5;
>     rv32imacfdcpu->X[16] = &rv32imacfdcpu->A6;
>     rv32imacfdcpu->X[17] = &rv32imacfdcpu->A7;
>     rv32imacfdcpu->X[18] = &rv32imacfdcpu->S2;
>     rv32imacfdcpu->X[19] = &rv32imacfdcpu->S3;
>     rv32imacfdcpu->X[20] = &rv32imacfdcpu->S4;
>     rv32imacfdcpu->X[21] = &rv32imacfdcpu->S5;
>     rv32imacfdcpu->X[22] = &rv32imacfdcpu->S6;
>     rv32imacfdcpu->X[23] = &rv32imacfdcpu->S7;
>     rv32imacfdcpu->X[24] = &rv32imacfdcpu->S8;
>     rv32imacfdcpu->X[25] = &rv32imacfdcpu->S9;
>     rv32imacfdcpu->X[26] = &rv32imacfdcpu->S10;
>     rv32imacfdcpu->X[27] = &rv32imacfdcpu->S11;
>     rv32imacfdcpu->X[28] = &rv32imacfdcpu->T3;
>     rv32imacfdcpu->X[29] = &rv32imacfdcpu->T4;
>     rv32imacfdcpu->X[30] = &rv32imacfdcpu->T5;
>     rv32imacfdcpu->X[31] = &rv32imacfdcpu->T6;
>     rv32imacfdcpu->CSR[768] = &rv32imacfdcpu->MSTATUS;
>     rv32imacfdcpu->CSR[772] = &rv32imacfdcpu->MIE;
>     rv32imacfdcpu->CSR[836] = &rv32imacfdcpu->MIP;
90a169,170
>     rv32imacfdcpu->PRIV = 3ULL;
>     rv32imacfdcpu->DPC = 0LL;
99,100d178
<     rv32imacfdcpu->PRIV = 3ULL;
<     rv32imacfdcpu->DPC = 0LL;
diff -r -I '^ \* Generated on .*' cdsl/gen_output/top/RV32IMACFD/RV32IMACFDArchSpecificImp.h cdsl/compare/top/RV32IMACFD/RV32IMACFDArchSpecificImp.h
41c41
<             128.0
---
>             4
55c55
<             128.0
---
>             4
diff -r -I '^ \* Generated on .*' cdsl/gen_output/top/RV32IMACFD/RV32IMACFDFuncs.c cdsl/compare/top/RV32IMACFD/RV32IMACFDFuncs.c
23c23
< mask = mask | 5767458LL;
---
> mask = mask | 5767458ULL;
45c45
< etiss_uint32 mask = 6280LL;
---
> etiss_uint32 mask = 6280ULL;
78c78
< return *((RV32IMACFD*)cpu)->CSR[768LL] | 8589934592LL | 34359738368LL;
---
> return *((RV32IMACFD*)cpu)->CSR[768LL] | 8589934592ULL | 34359738368ULL;
206c206
< ((RV32IMACFD*)cpu)->PRIV = (1LL) & 0x7ULL;
---
> ((RV32IMACFD*)cpu)->PRIV = (1ULL) & 0x7ULL;
220c220
< ((RV32IMACFD*)cpu)->PRIV = (3LL) & 0x7ULL;
---
> ((RV32IMACFD*)cpu)->PRIV = (3ULL) & 0x7ULL;
283,284c283,284
< if (enabled_interrupts >> 12LL) { // conditional
< enabled_interrupts = enabled_interrupts >> 12LL << 12LL;
---
> if (enabled_interrupts >> 12ULL) { // conditional
> enabled_interrupts = enabled_interrupts >> 12ULL << 12ULL;
diff -r -I '^ \* Generated on .*' cdsl/gen_output/top/RV32IMACFD/RV32IMACFD.h cdsl/compare/top/RV32IMACFD/RV32IMACFD.h
54a55,56
>         etiss_uint32 FENCE[8];
>         etiss_uint8 RES[8];
57,59d58
<         etiss_uint32 RES_ADDR;
<         etiss_uint32 FENCE[8];
<         etiss_int8 RES[8];
64a64
>         etiss_uint32 RES_ADDR;
diff -r -I '^ \* Generated on .*' cdsl/gen_output/top/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp cdsl/compare/top/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
3342c3342
< cp.code() += "((RV32IMACFD*)cpu)->FENCE[0LL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
---
> cp.code() += "((RV32IMACFD*)cpu)->FENCE[0ULL] = " + std::to_string(pred << 4ULL | succ) + "ULL;\n";
diff -r -I '^ \* Generated on .*' cdsl/gen_output/top/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp cdsl/compare/top/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
185c185
< cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1LL;\n";
---
> cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1ULL;\n";

[PhilippvK]

How can I test this @PhilippvK

do you mean how to run the RISCV ISA Test suite on the generated ETISS arch? I can provide an example test script which I use until Friday…

For the more special features which are only used by non-standard extensions we will have to come up with our own tests, which can be probably integrated in the etiss_riscv_examples repo

[jokap11]

How can I test this @PhilippvK

do you mean how to run the RISCV ISA Test suite on the generated ETISS arch? I can provide an example test script which I use until Friday…

I think that should suffice for now. I also don't expect any behavioral differences, since the changes are minimal compared to my generated code.

I just want to merge this here somewhat fast, so that I can fork properly

[PhilippvK]

@jokap11

Here are the instructions to run the RISC-V test Suite using ETISS:

# Prerequisites:
# Download RISC-V multilib toolchain and add to PATH

# Setup ETISS RISC-V Test Runner
git clone git@github.com:tum-ei-eda/etiss_riscv_tests.git
cd etiss_riscv_tests
python3 -m venv venv
source venv/bin/activate
pip install -r requirements.txt
cd ..

# Setup ETISS
git clone https://github.com/tum-ei-eda/etiss
cd etiss
cd PluginImpl
ln -s ../../etiss_riscv_tests/FileLoggerPlugin .
cd ..
cmake -S . -B build -DCMAKE_BUILD_TYPE=Debug
cmake --build build -j`nproc`
export ETISS_BUILD_DIR=$(pwd)/build

cd ..

# Setup RISC-V test suite
git clone https://github.com/riscv-software-src/riscv-tests.git
cd riscv-tests
git submodule update --init --recursive .
autoconf
./configure
make RISCV_PREFIX=riscv64-unknown-elf- XLEN=32 isa -j `nproc`
cd ..

# Run Tests
python etiss_riscv_tests/test.py --arch RV32IMACFD --bits 32 --ext IMACFD --virt p --timeout 10 --jit tcc --runlevel msu riscv-tests/isa $ETISS_BUILD_DIR/bin/bare_etiss_processor

# Check Results
# ls results_250618_105936_32-msu-imacfd-p_RV32IMACFD/
# cat results_250618_105936_32-msu-imacfd-p_RV32IMACFD/fail.txt
# cat results_250618_105936_32-msu-imacfd-p_RV32IMACFD/pass.txt
# ...

The should be 5 failing tests, which is expected:

summary:
executed 104 tests
failed: 5

[jokap11]

@PhilippvK Ready for take off?

[jokap11]

Superseded by #98