Testbench initialization

[eselznick2]

SFR Edit- Moving summary for changes from email into this PR (2026-04-14)

Change Summary

ClockDivider2X.vhd

• Major change: renamed entity to ClockDivider2XPorts / ClockDivider2X, and changed phase split (eg div is 10, it was high for 5,6,7,8,9,0 and low 1,2,3,4)

PatternFinder.vhd

• Major change: cleanup ('00' -> "00")

PeekRingBuffer.vhd

• Major change: compile/syntax and assignment fixes (duplicate PopAddress declaration removed, missing parens fixed, signal assignment operator fixes for LastHeaderEnd/LastFooterEnd).
• Question: TB shows current full/empty/count behavior effectively gives 2047 usable bytes in a 2048 address (shows full after 2047 writes). If this is intended then fine, idk if full 2048 needed.
• Question: empty, full, and count do calculations using U/X before they can be reset and this gives assertion warnings, sim still runs / assuming this setup won't mess up syn.

RtcCounter.vhd

• Major change: GeneratedPPS moved into registered process behavior, sensitivity cleanup, and reset handling tightened (SetChangedTime/GeneratedPPS reset behavior made explicit).

UartRxFifoExtClk.vhd

• Major change: switched FIFO instance from gated_fifo interface to fifo interface (wone_i/rone_i to we_i/re_i) with wiring cleanup.

UartRxFifoExtClkPeek.vhd

• Major change: updated internal PeekRingBuffer component declaration/map with LastHeaderEnd, LastFooterEnd, PayloadLen, HeaderFooterPayloadLenMatches, currently tied to internal Unused* signals.

UartRxFifoParity.vhd

• Major change: If ParityErr goes high, then no write to fifo

UartRxParity.vhd

• Major change: receive logic update to more closely match UartRxRaw logic (PARITY_EVEN generic, parity accumulation/check, stop-bit/parity handling, ParityErr output behavior).

UartTxParity.vhd

• Major change: Go edge is now accepted only when Busy = 0 (prevents retrigger while active).

VariableClockDivider2X.vhd

• Major change: renamed entity/arch to VariableClockDivider2XPorts / VariableClockDivider2X and adjusted phase logic around terminal_count handling (same as non variable)

VariableOneShot.vhd

• Major change: rm /2 out of bounds.

crc_fifo.vhd

• Major change: Added generic reset value to crc value (default is xFFFFFFFF).

fifo_gen.vhd

• Major change: read/write gate logic rewritten to avoid U/X, count output now combinational from state (can prob just be written straight from counter_r), full/empty boundary equations adjusted (empty/full etc... based on incoming read/write) so update on next edge, read output reset behavior (if we don't need empty/full/count logic immediatley on next I can revert this logic)

fifo_peek.vhd

• Major change: Peek from RAM, reset-safe read outputs, same empty/full/count logic as fifo_gen.vhd

gated_fifo.vhd

• Major change: N/A
• Question: Write is not tied to data_i so you could request a write, let it reach the fifo, and change data_i to write wrong data. Should write data be registered with a write?

gated_fifo_peek.vhd

• Major change: aligned with new fifo_peek
• Question: same data_i question as gated_fifo.vhd

CGraphTypes.vhd

• Major change: N/A

ClockDivider.vhd

• Major change: N/A

crc_byte.vhd

• Major change: N/A

crc_stream.vhd

• Major change: N/A

FieldLatcher.vhd

• Major change: N/A

IBufP1.vhd

• Major change: N/A

IBufP2.vhd

• Major change: N/A
• Question: This is used in a lot of different UartFifo implementations. But because the buf has no reset value, if there is a high value within the buffer when a reset hits, this high value will still propogate and can cause some wrong post-reset logic (like writing zero immediately after reset). If we're only expecting rst at initialization, this is fine, but if we're expecting some mid-run rst then it might be worth to add a generic rst value to buffers.

IBufP3.vhd

• Major change: N/A

OneShot.vhd

• Major change: N/A

PeekRam.vhd

• Major change: N/A

PPSCount.vhd

• Major change: N/A

UartRx.vhd

• Major change: N/A

UartRxExtClk.vhd

• Major change: N/A

UartRxRaw.vhd

• Major change: N/A

UartTx.vhd

• Major change: N/A

UartTxFifo.vhd

• Major change: change component name for sim

UartTxFifoExtClk.vhd

• Major change: N/A

UartTxFifoParity.vhd

• Major change: N/A

VariableClockDivider.vhd

• Major change: N/A

Testbench Overview

Clock/Timing Dividers

ClockDivider_tb.vhd

• Reset polarity and initial state checks across configs.
• Confirms expected divide cadence (for example /10 and /6 behavior).
• Also tested mid-run resets from both output phases.

ClockDivider2X_tb.vhd

• Same core checks as ClockDivider_tb.vhd, but for the 2X path.
• Focus here is the updated phase split behavior plus reset recovery.

VariableClockDivider_tb.vhd

• Mainly to make sure programmable terminal count still behaves like the fixed divider.
• Retune-at-runtime cases are covered (no reset in between).
• Includes terminal-count edge cases.

VariableClockDivider2X_tb.vhd

• Same idea as VariableClockDivider_tb.vhd, applied to the 2X implementation.
• Checks dynamic terminal-count changes and reset recovery.

One-Shot Pulsing

OneShot_tb.vhd

• Reset behavior plus trigger/pretrigger timing checks.
• Exercises delay variants and one-shot latch/retrigger boundaries.
• Includes reset-before-trigger and reset-after-trigger paths.

VariableOneShot_tb.vhd

• Programmable delay values (small/normal/large).
• Covers delay changes before trigger, pretrigger variants, and reset recovery.

UART RX / RX FIFO

UartRx_tb.vhd

• Basic decode, back-to-back bytes, and byte-range traffic.
• Reset-during-reception and break-condition handling.
• Checks completion signaling and output hold behavior.

UartRxRaw_tb.vhd

• Make sure sampling/enable gating and stop-bit timing rules hold.
• Basic decode, full byte range, completion signals (normal behavior)
• Includes baud mismatch, back-to-back frames, and reset mid-frame.

UartRxExtClk_tb.vhd

• Same coverage style as UartRx_tb.vhd, but with external clocking.
• Also checks ext-clock-specific stop-bit timing thresholds.

UartRxParity_tb.vhd

• Parity mode matrix (odd/even), parity accumulation, and parity error signaling.
• Stop-bit timing and baud mismatch cases.
• Reset during active frame is covered too.

UartRxFifoExtClk_tb.vhd

• This one is mostly about FIFO integration after the interface swap.
• Single/burst/overlap traffic, read-while-write behavior, and drain ordering.
• Full/empty boundaries plus resets with buffered data and active frames.

UartRxFifoExtClkPeek_tb.vhd

• Adds peek + multipop coverage on top of RX FIFO behavior.
• Pop-to-empty/refill/full-to-empty sequences are included.
• Also checks simultaneous pop+write and skip/address edge cases.

UartRxFifoParity_tb.vhd

• Main check here: bad parity frames do not get written into FIFO.
• Includes good/bad mixed streams, read timing overlap, boundaries, and reset recovery.

UART TX / TX FIFO

UartTx_tb.vhd

• Reset/idle and normal TX data transmission.
• Go/Busy interaction (no accidental retrigger while busy).
• Reset during transmission is covered.

UartTxParity_tb.vhd

• Same core TX checks as UartTx_tb.vhd, with parity framing enabled.
• Mainly to confirm Busy-gated Go behavior stays solid with parity enabled.
• Sending correct Parity bit under heavy load.

UartTxFifo_tb.vhd

• Covers FIFO fed TX flow from empty to queued multi-byte sends.
• Verifies CTS blocking/unblocking behavior and handoff timing.
• Includes full-queue boundaries and reset during queued transmission.

UartTxFifoExtClk_tb.vhd

• Covers FIFO fed TX flow from empty to queued multi-byte sends under external clk.
• Verifies CTS blocking/unblocking behavior and handoff timing.
• Includes full-queue boundaries and reset during queued/active transmission.

UartTxFifoParity_tb.vhd

• Parity FIFO TX flow under single/queued sends.
• CTS gating, queue boundaries, and reset during active transmission are all covered.

FIFO / Peek

fifo_gen_tb.vhd

• Core FIFO baseline: reset, normal read/write, burst traffic, and boundaries.
• Simultaneous read/write is exercised across empty, steady-state, near-full, and full.
• r_ack timing and reset behavior during active traffic are checked.

fifo_peek_tb.vhd

• Adds peek + multipop coverage on top of basic FIFO behavior.
• Tests wraparound (still a bit fishy), skip logic, and mixed read/write traffic.
• Includes overlap edge cases (empty, near full, full).
• Also re-checks behavior after resets.

gated_fifo_tb.vhd

• Same FIFO boundary/read-write checks, but with edge-triggered strobes.
• Includes held-high strobe behavior and r_ack handling.

gated_fifo_peek_tb.vhd

• gated_fifo_tb coverage plus peek/multipop behavior.
• Mainly to make sure gated strobes do not break skip/peek paths.

PeekRam_tb.vhd

• Straightforward RAM checks: write/read/overwrite/same-cycle interactions.
• No-write-when-disabled and reset-after-write behavior included.

PeekRingBuffer_tb.vhd

• This one is mostly about correctness around tricky ring-buffer edges.
• Reset defaults, wrap, full/empty transitions, and pop advancement are all exercised.
• Header/footer marker and metadata updates are explicitly checked (not fully done yet).
• TB also exposes the current one-slot-empty behavior (2047 usable entries at depth 2048).

CRC / Pattern / Latching / Counters

crc_byte_tb.vhd

• Quick check that byte-wise CRC combinational logic matches reference vectors.

crc_stream_tb.vhd

• Stream CRC checks over reset, zero stream, and simple text payload cases.

crc_fifo_tb.vhd

• Deeper coverage here since this block has more moving parts.
• CRC over varied patterns (zeros, ones, PRNG, address slices).
• Full-range sweep plus back-to-back runs without reset.
• Reset handling is tested, including reset during active CRC computation.

PatternFinder_tb.vhd (in progress)

• Steps through match/mismatch cases for the pattern detector.
• Makes sure it recovers correctly after a bad sequence.
• Also checks reset behavior mid-stream.

FieldLatcher_tb.vhd

• Byte capture and shift sequencing checks across multi-byte fields.
• Also covers held write-request behavior and reset timing cases.

RtcCounter_tb.vhd

• Free-run ms/sec progression and rollover checks.
• PPS sync/grace timing, SetTime handling, and generated PPS behavior.

PPSCount_tb.vhd

• Simple reset + nominal PPS counting checks.

Small TypeTBs

CGraphTypes_tb.vhd

• Quick type/package checks (so the CGraphTypes.vhd can be built).

IBufP1_tb.vhd, IBufP2_tb.vhd, IBufP3_tb.vhd

• Simple sanity checks that values propagate through the buffers correctly.

Full Catalog:
Each test for each tb and what exactly it is testing
testbench_test_catalog.md